Lines Matching +full:0 +full:x1004
20 #define CX_GMU_CBCR_SLEEP_MASK 0xF
22 #define CX_GMU_CBCR_WAKE_MASK 0xF
33 { 249600000, 2000000000, 0 },
37 .offset = 0x100,
54 { P_BI_TCXO, 0 },
68 F(19200000, P_BI_TCXO, 1, 0, 0),
69 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
74 .cmd_rcgr = 0x1120,
75 .mnd_width = 0,
89 .halt_reg = 0x107c,
92 .enable_reg = 0x107c,
93 .enable_mask = BIT(0),
102 .halt_reg = 0x1098,
105 .enable_reg = 0x1098,
106 .enable_mask = BIT(0),
120 .halt_reg = 0x108c,
123 .enable_reg = 0x108c,
124 .enable_mask = BIT(0),
133 .halt_reg = 0x1004,
136 .enable_reg = 0x1004,
137 .enable_mask = BIT(0),
146 .halt_reg = 0x109c,
149 .enable_reg = 0x109c,
150 .enable_mask = BIT(0),
159 .gdscr = 0x106c,
160 .gds_hw_ctrl = 0x1540,
170 .gdscr = 0x100c,
171 .clamp_io_ctrl = 0x1508,
199 .max_register = 0x8008,
228 gpu_cc_pll_config.l = 0x12; in gpu_cc_sc7180_probe()
229 gpu_cc_pll_config.alpha = 0xc000; in gpu_cc_sc7180_probe()
230 gpu_cc_pll_config.config_ctl_val = 0x20485699; in gpu_cc_sc7180_probe()
231 gpu_cc_pll_config.config_ctl_hi_val = 0x00002067; in gpu_cc_sc7180_probe()
232 gpu_cc_pll_config.user_ctl_val = 0x00000001; in gpu_cc_sc7180_probe()
233 gpu_cc_pll_config.user_ctl_hi_val = 0x00004805; in gpu_cc_sc7180_probe()
234 gpu_cc_pll_config.test_ctl_hi_val = 0x40000000; in gpu_cc_sc7180_probe()
241 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; in gpu_cc_sc7180_probe()
242 regmap_update_bits(regmap, 0x1098, mask, value); in gpu_cc_sc7180_probe()