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/nrf52832-nimble/packages/NimBLE-latest/apps/ext_advertiser/src/
H A Dpatterns.h21 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0x0a,
22 0x00, 0x0c, 0x00, 0x0e, 0x00, 0x10, 0x00, 0x12, 0x00, 0x14,
23 0x00, 0x16, 0x00, 0x18, 0x00, 0x1a, 0x00, 0x1c, 0x00, 0x1e,
24 0x00, 0x20, 0x00, 0x22, 0x00, 0x24, 0x00, 0x26, 0x00, 0x28,
25 0x00, 0x2a, 0x00, 0x2c, 0x00, 0x2e, 0x00, 0x30, 0x00, 0x32,
26 0x00, 0x34, 0x00, 0x36, 0x00, 0x38, 0x00, 0x3a, 0x00, 0x3c,
27 0x00, 0x3e, 0x00, 0x40, 0x00, 0x42, 0x00, 0x44, 0x00, 0x46,
28 0x00, 0x48, 0x00, 0x4a, 0x00, 0x4c, 0x00, 0x4e, 0x00, 0x50,
29 0x00, 0x52, 0x00, 0x54, 0x00, 0x56, 0x00, 0x58, 0x00, 0x5a,
30 0x00, 0x5c, 0x00, 0x5e, 0x00, 0x60, 0x00, 0x62, 0x00, 0x64,
[all …]
/nrf52832-nimble/rt-thread/libcpu/mips/common/
H A Dmips_context.h33 #define FPU_ADJ 0
58 sw $0, ( 0 * 4)(sp)
119 sw t0 , 0x00(a0)
120 swc1 $f0,(0x04 * 1)(a0)
121 swc1 $f1,(0x04 * 2)(a0)
122 swc1 $f2,(0x04 * 3)(a0)
123 swc1 $f3,(0x04 * 4)(a0)
124 swc1 $f4,(0x04 * 5)(a0)
125 swc1 $f5,(0x04 * 6)(a0)
126 swc1 $f6,(0x04 * 7)(a0)
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/test/unit/mdns/
H A Dtest_mdns.c41 static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x00 }; in START_TEST()
50 offset = mdns_readname(p, 0, &domain); in START_TEST()
60 …static const u8_t data[] = { 0x05, 0x00, 0xFF, 0x08, 0xc0, 0x0f, 0x04, 0x7f, 0x80, 0x82, 0x88, 0x0… in START_TEST()
69 offset = mdns_readname(p, 0, &domain); in START_TEST()
79 static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a' }; in START_TEST()
88 offset = mdns_readname(p, 0, &domain); in START_TEST()
97 0x05, 'm', 'u', 'l', 't', 'i', in START_TEST()
98 0x52, 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', in START_TEST()
103 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 0x00 in START_TEST()
113 offset = mdns_readname(p, 0, &domain); in START_TEST()
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/test/unit/mdns/
H A Dtest_mdns.c41 static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a', 's', 't', 0x00 }; in START_TEST()
50 offset = mdns_readname(p, 0, &domain); in START_TEST()
60 …static const u8_t data[] = { 0x05, 0x00, 0xFF, 0x08, 0xc0, 0x0f, 0x04, 0x7f, 0x80, 0x82, 0x88, 0x0… in START_TEST()
69 offset = mdns_readname(p, 0, &domain); in START_TEST()
79 static const u8_t data[] = { 0x05, 'm', 'u', 'l', 't', 'i', 0x04, 'c', 'a' }; in START_TEST()
88 offset = mdns_readname(p, 0, &domain); in START_TEST()
97 0x05, 'm', 'u', 'l', 't', 'i', in START_TEST()
98 0x52, 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', in START_TEST()
103 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 0x00 in START_TEST()
113 offset = mdns_readname(p, 0, &domain); in START_TEST()
[all …]
/nrf52832-nimble/rt-thread/components/drivers/spi/
H A Denc28j60.h21 // - Register address (bits 0-4)
24 #define ADDR_MASK 0x1F
25 #define BANK_MASK 0x60
26 #define SPRD_MASK 0x80
28 #define EIE 0x1B
29 #define EIR 0x1C
30 #define ESTAT 0x1D
31 #define ECON2 0x1E
32 #define ECON1 0x1F
33 // Bank 0 registers
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/cortex-m4/
H A Dcontext_iar.S21 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
22 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
23 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
24 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
97 ; clear rt_thread_switch_interrupt_flag to 0
98 MOV r1, #0x00
108 TST lr, #0x10 ; if(!EXC_RETURN[4])
117 MOV r4, #0x00 ; flag = 0
118 TST lr, #0x10 ; if(!EXC_RETURN[4])
[all …]
H A Dcontext_rvds.S20 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
21 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
22 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
23 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
100 ; clear rt_thread_switch_interrupt_flag to 0
101 MOV r1, #0x00
111 TST lr, #0x10 ; if(!EXC_RETURN[4])
118 MOV r4, #0x00 ; flag = 0
120 TST lr, #0x10 ; if(!EXC_RETURN[4])
[all …]
H A Dcontext_gcc.S25 .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
26 .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
27 .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
28 .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
29 .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
98 /* clear rt_thread_switch_interrupt_flag to 0 */
99 MOV r1, #0x00
109 TST lr, #0x10 /* if(!EXC_RETURN[4]) */
116 MOV r4, #0x00 /* flag = 0 */
118 TST lr, #0x10 /* if(!EXC_RETURN[4]) */
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/cortex-m7/
H A Dcontext_iar.S21 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
22 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
23 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
24 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
97 ; clear rt_thread_switch_interrupt_flag to 0
98 MOV r1, #0x00
108 TST lr, #0x10 ; if(!EXC_RETURN[4])
117 MOV r4, #0x00 ; flag = 0
118 TST lr, #0x10 ; if(!EXC_RETURN[4])
[all …]
H A Dcontext_rvds.S20 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
21 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
22 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
23 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
100 ; clear rt_thread_switch_interrupt_flag to 0
101 MOV r1, #0x00
111 TST lr, #0x10 ; if(!EXC_RETURN[4])
118 MOV r4, #0x00 ; flag = 0
120 TST lr, #0x10 ; if(!EXC_RETURN[4])
[all …]
H A Dcontext_gcc.S25 .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
26 .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
27 .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
28 .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
29 .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
98 /* clear rt_thread_switch_interrupt_flag to 0 */
99 MOV r1, #0x00
109 TST lr, #0x10 /* if(!EXC_RETURN[4]) */
116 MOV r4, #0x00 /* flag = 0 */
118 TST lr, #0x10 /* if(!EXC_RETURN[4]) */
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/test/unit/dhcp/
H A Dtest_dhcp.c11 static const u8_t broadcast[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
13 static const u8_t magic_cookie[] = { 0x63, 0x82, 0x53, 0x63 };
16 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, /* To unit */
17 0x00, 0x0F, 0xEE, 0x30, 0xAB, 0x22, /* From Remote host */
18 0x08, 0x00, /* Protocol: IP */
19 …0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00, 0x80, 0x11, 0x36, 0xcc, 0xc3, 0xaa, 0xbd, 0xab, 0x…
20 0x00, 0x43, 0x00, 0x44, 0x01, 0x34, 0x00, 0x00, /* UDP header */
22 0x02, /* Type == Boot reply */
23 0x01, 0x06, /* Hw Ethernet, 6 bytes addrlen */
24 0x00, /* 0 hops */
[all …]
/nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/test/unit/dhcp/
H A Dtest_dhcp.c11 static const u8_t broadcast[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
13 static const u8_t magic_cookie[] = { 0x63, 0x82, 0x53, 0x63 };
16 0x00, 0x23, 0xc1, 0xde, 0xd0, 0x0d, /* To unit */
17 0x00, 0x0F, 0xEE, 0x30, 0xAB, 0x22, /* From Remote host */
18 0x08, 0x00, /* Protocol: IP */
19 …0x45, 0x10, 0x01, 0x48, 0x00, 0x00, 0x00, 0x00, 0x80, 0x11, 0x36, 0xcc, 0xc3, 0xaa, 0xbd, 0xab, 0x…
20 0x00, 0x43, 0x00, 0x44, 0x01, 0x34, 0x00, 0x00, /* UDP header */
22 0x02, /* Type == Boot reply */
23 0x01, 0x06, /* Hw Ethernet, 6 bytes addrlen */
24 0x00, /* 0 hops */
[all …]
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/include/host/
H A Dble_sm.h30 #define BLE_SM_ERR_PASSKEY 0x01
31 #define BLE_SM_ERR_OOB 0x02
32 #define BLE_SM_ERR_AUTHREQ 0x03
33 #define BLE_SM_ERR_CONFIRM_MISMATCH 0x04
34 #define BLE_SM_ERR_PAIR_NOT_SUPP 0x05
35 #define BLE_SM_ERR_ENC_KEY_SZ 0x06
36 #define BLE_SM_ERR_CMD_NOT_SUPP 0x07
37 #define BLE_SM_ERR_UNSPECIFIED 0x08
38 #define BLE_SM_ERR_REPEATED 0x09
39 #define BLE_SM_ERR_INVAL 0x0a
[all …]
H A Dble_hs_adv.h45 /*** 0x01 - Flags. */
48 /*** 0x02,0x03 - 16-bit service class UUIDs. */
53 /*** 0x04,0x05 - 32-bit service class UUIDs. */
58 /*** 0x06,0x07 - 128-bit service class UUIDs. */
63 /*** 0x08,0x09 - Local name. */
68 /*** 0x0a - Tx power level. */
72 /*** 0x0d - Slave connection interval range. */
75 /*** 0x16 - Service data - 16-bit UUID. */
79 /*** 0x17 - Public target address. */
83 /*** 0x19 - Appearance. */
[all …]
H A Dble_att.h37 #define BLE_ATT_UUID_PRIMARY_SERVICE 0x2800
38 #define BLE_ATT_UUID_SECONDARY_SERVICE 0x2801
39 #define BLE_ATT_UUID_INCLUDE 0x2802
40 #define BLE_ATT_UUID_CHARACTERISTIC 0x2803
42 #define BLE_ATT_ERR_INVALID_HANDLE 0x01
43 #define BLE_ATT_ERR_READ_NOT_PERMITTED 0x02
44 #define BLE_ATT_ERR_WRITE_NOT_PERMITTED 0x03
45 #define BLE_ATT_ERR_INVALID_PDU 0x04
46 #define BLE_ATT_ERR_INSUFFICIENT_AUTHEN 0x05
47 #define BLE_ATT_ERR_REQ_NOT_SUPPORTED 0x06
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/cortex-m3/
H A Dcontext_iar.S19 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
20 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
21 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
22 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
95 ; clear rt_thread_switch_interrupt_flag to 0
96 MOV r1, #0x00
120 ORR lr, lr, #0x04
132 ; set from thread to 0
134 MOV r0, #0x0
[all …]
H A Dcontext_rvds.S18 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
19 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
20 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
21 NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
22 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
98 ; clear rt_thread_switch_interrupt_flag to 0
99 MOV r1, #0x00
123 ORR lr, lr, #0x04
138 ; set from thread to 0
140 MOV r0, #0x0
[all …]
H A Dcontext_gcc.S22 .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
23 .equ ICSR, 0xE000ED04 /* interrupt control state register */
24 .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
26 .equ SHPR3, 0xE000ED20 /* system priority register (3) */
27 .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
95 /* clear rt_thread_switch_interrupt_flag to 0 */
96 MOV R1, #0
120 ORR LR, LR, #0x04
133 /* set from thread to 0 */
135 MOV R0, #0
[all …]
/nrf52832-nimble/rt-thread/libcpu/arm/lpc24xx/
H A DLPC24xx.h18 #define USERMODE 0x10
19 #define FIQMODE 0x11
20 #define IRQMODE 0x12
21 #define SVCMODE 0x13
22 #define ABORTMODE 0x17
23 #define UNDEFMODE 0x1b
24 #define MODEMASK 0x1f
25 #define NOINT 0xc0
30 #define VIC_BASE_ADDR 0xFFFFF000
31 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
[all …]
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/test/src/
H A Dble_sm_lgcy_test.c51 0xe1, 0xfc, 0xda, 0xf4, 0xb7, 0x6c, in TEST_CASE()
54 0x33, 0x22, 0x11, 0x00, 0x45, 0x0a, in TEST_CASE()
57 .io_cap = 0x04, in TEST_CASE()
58 .oob_data_flag = 0x00, in TEST_CASE()
59 .authreq = 0x05, in TEST_CASE()
60 .max_enc_key_size = 0x10, in TEST_CASE()
61 .init_key_dist = 0x07, in TEST_CASE()
62 .resp_key_dist = 0x07, in TEST_CASE()
65 .io_cap = 0x03, in TEST_CASE()
66 .oob_data_flag = 0x00, in TEST_CASE()
[all …]
H A Dble_sm_sc_test.c40 * Initiator address type: 0
41 * Responder address type: 0
51 0xca, 0x61, 0xa0, 0x67, 0x94, 0xe0, in TEST_CASE()
54 0x33, 0x22, 0x11, 0x00, 0x45, 0x0a, in TEST_CASE()
57 .io_cap = 0x03, in TEST_CASE()
58 .oob_data_flag = 0x00, in TEST_CASE()
59 .authreq = 0x09, in TEST_CASE()
60 .max_enc_key_size = 0x10, in TEST_CASE()
61 .init_key_dist = 0x0d, in TEST_CASE()
62 .resp_key_dist = 0x0f, in TEST_CASE()
[all …]
/nrf52832-nimble/rt-thread/components/drivers/usb/usbdevice/class/
H A Dhid.h18 #define HID_DESCRIPTOR_TYPE 0x21
19 #define HID_DESCRIPTOR_SIZE 0x09
20 #define HID_OFF_HID_DESC 0x12
22 #define USB_HID_SUBCLASS_BOOT 0x01
23 #define USB_HID_SUBCLASS_NOBOOT 0x00
25 #define USB_HID_PROTOCOL_NONE 0x00
26 #define USB_HID_PROTOCOL_KEYBOARD 0x01
27 #define USB_HID_PROTOCOL_MOUSE 0x02
30 #define USB_HID_REQ_GET_REPORT 0x01
31 #define USB_HID_REQ_GET_IDLE 0x02
[all …]
/nrf52832-nimble/rt-thread/components/drivers/include/drivers/
H A Dpin.h29 #define PIN_LOW 0x00
30 #define PIN_HIGH 0x01
32 #define PIN_MODE_OUTPUT 0x00
33 #define PIN_MODE_INPUT 0x01
34 #define PIN_MODE_INPUT_PULLUP 0x02
35 #define PIN_MODE_INPUT_PULLDOWN 0x03
36 #define PIN_MODE_OUTPUT_OD 0x04
38 #define PIN_IRQ_MODE_RISING 0x00
39 #define PIN_IRQ_MODE_FALLING 0x01
40 #define PIN_IRQ_MODE_RISING_FALLING 0x02
[all …]
/nrf52832-nimble/rt-thread/components/net/sal_socket/include/
H A Dsal_netdb.h30 #define AI_PASSIVE 0x01
31 #define AI_CANONNAME 0x02
32 #define AI_NUMERICHOST 0x04
33 #define AI_NUMERICSERV 0x08
34 #define AI_V4MAPPED 0x10
35 #define AI_ALL 0x20
36 #define AI_ADDRCONFIG 0x40
39 #define AI_PASSIVE 0x01
40 #define AI_CANONNAME 0x02
41 #define AI_NUMERICHOST 0x04
[all …]

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