fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:https://github.com/OpenXiangShan/XiangShan/issues/4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>

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style(Bundles): move bundles to Bundles.scala (#4247)

area(LoadQueue): remove useless regs (#4062)

Vector Load's additional release logic in the `RAR/RAW Queue` looks
unneeded, which would result in the `RAR/RAW Queue` storing redundant
`regs` for `uop

area(LoadQueue): remove useless regs (#4062)

Vector Load's additional release logic in the `RAR/RAW Queue` looks
unneeded, which would result in the `RAR/RAW Queue` storing redundant
`regs` for `uopidx`.

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feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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area(Lsq): compress rar/raw paddr and remove sq useless regs (#3976)

* LoadQueueRAR PAddr hash function, total 16bits:
![vaddr_compress](https://github.com/user-attachments/assets/6b87fb4d-7080-4b5

area(Lsq): compress rar/raw paddr and remove sq useless regs (#3976)

* LoadQueueRAR PAddr hash function, total 16bits:
* LoadQueueRAW use PAddr[29:6], total 24bits

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LoadQueueRAW: need check only when storeIn is valid

* If storeIn is not valid, the bits in storeIn means nothing. Using bits when valid is not asserted will cause X propagation.

LSQ: optimize static clock gating coverage and fix x_value in vcs (#3176)

optimize LSQ static clock gating coverage, fix x_value in vcs

MemBlock: refactor selectOldest of rollback for better timing

Don't select oldest rollback twice in LoadQueueRAW, send to memblock select oldest with other, will have port to send rollback request

MemBlock: refactor selectOldest of rollback for better timing

Don't select oldest rollback twice in LoadQueueRAW, send to memblock select oldest with other, will have port to send rollback request to memblock in LoadQueueRAW.

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LoadQueueRAW: use grouped instead of sliding

LoadQueueRAW: simplify group logic

Revert "LSQ: optimize static clock gating coverage (#3023)" (#3055)

LSQ: refactor vector load/store commit judging logic to fix X in vcs (#3048)

clockgate: set default initialization with 0 to fix X in vcs (#3031)

LSQ: optimize static clock gating coverage (#3023)

Merge branch 'master' into vlsu-tmp-master

VLSU, lsq: support more than one vector pipeline

rv64v: implement lsu & lsq vector datapath

delay paddr/mask check one more cycle

fix merge error

Merge remote-tracking branch 'upstream/master' into backendq

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

* memblock: add a Reg between inner/outer reset_vec

* missqueue: make mem_grant always ready

* Enable ECC path again

* remove fast replay reorder logic

* l1pf: use chosen of arbiter to improve timing

* remove reorder remain logic

* mq: use ParallelORR instead of orR

* Strengthen the conditions for load to load path for timing

* fix load to load data select for timing

* refactoring lq replay valid logic

* fix replay port

* fix load unit s0 arbitor logic

* add topdown wiring

* fix ldu ecc path

* remove lateKill

* ecc: physically remove ecc in DataArray

* loadpipe: use ParallelORR and ParallelMux for timing

* mainpipe: use ParallelMux and ParallelorR for timing

* fix fast replay is killed at s1

* fix replay cancel logic

* fix mq nack feedback logic

* sms: fix pf queue tlb req logic for timing

* kill load at s1

* fix loadqueuereplay enq logic

* opt raw rollback arbiter logic

* fix ecc_delayed writeback logic

* train all l1 pf and sms at load s3 for better timing

* disable load to load forward

* Revert "kill load at s1"

This reverts commit 56d47582ad4dd9c83373fb2db2a0709075485d4d.

* fix s0 kill logic

* ITLBRepeater: Add one more buffer when PTW resp

* remove trigger

* fix feedback_slow logic

* add latch in uncachebuffer rollback

* remove trigger in port

* fast replay: use dcache ready

* fix replay logic at s1

* uncache: fix uncache writeback

* fix delay kill logic

* fix clean exception loigc at s3

* fix ldu rollback logic

* fix ldu rollback valid logic

---------

Co-authored-by: sfencevma <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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Add VLSU

* miscs: optimize code style

* vector: add VLSU param system and redefine vector lq io

* VLUopQueue: add flow split and address generation logic

* VLUopQueue: add flow issue and writebac

Add VLSU

* miscs: optimize code style

* vector: add VLSU param system and redefine vector lq io

* VLUopQueue: add flow split and address generation logic

* VLUopQueue: add flow issue and writeback logic

* VLUopQueue: set vstart for elements with exception

* VLUopQueue: handle unit-stride fof loads

* VLUopQueue: implement vector masking according to vm

* vector: rewrite vector store io

* VlFlowQueue: add enqueue and dequeue logic

* VLFlowQueue: fix some coding problem

* VlFlowQueue: add issue, replay and result logic

* VLFlowQueue: add redirect logic

* Rob: fix compilation error

* vector: remove stale codes

* vector: add VSUopQueue and fix bugs for vector load

* backbone: add vector load/store execution paths

* VSFlowQueue: Basic function

* VLUopQueue: add redirect logic for load-load violation

* VSFlowQueue: fix some compile problems

* VSUopQueue: add signal to indicate whether a flow is the last one

* VSFlowQueue: inform scala sq when vector store finished

* StoreQueue: maintain sequential retirement between scalar & vector stores

* LoadQueueRAW: handle violation between vector stores & scalar loads

* LDU: add vector store to scalar load forwarding

* XSCore: fix writeback width of MemBlock

* vector: fix load/store whole register and masked unit-stride load/store emul, evl, flownum (#2383)

* VSFlowQueue: Support STLF

* VLFlowQueue: fix compile bug

* VSFlowQueue: fix compile problem

---------

Co-authored-by: xuzefan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: weidingliu <[email protected]>

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remove rawNuke (#2460)

Co-authored-by: Lyn <[email protected]>

LDU: fix rar flush logic (#2445)

* fix rar flush logic

* fix re-fetch and flushPipe logic

* fix rar rollback logic, cancel isFlushPipe

* fix syntax error

* fix selectOldest logic

* fi

LDU: fix rar flush logic (#2445)

* fix rar flush logic

* fix re-fetch and flushPipe logic

* fix rar rollback logic, cancel isFlushPipe

* fix syntax error

* fix selectOldest logic

* fix redirect pc gen loigc

---------

Co-authored-by: Lyn <[email protected]>

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Merge upstream/master into tmp-backend-merge-master