| #
bbfca13a |
| 25-Feb-2021 |
zoujr <[email protected]> |
perf: Add FPGAPlatform switch for perf counters
|
| #
1d32896e |
| 22-Jan-2021 |
jinyue110 <[email protected]> |
DecodeUnit/IFU: move RVC expander to frontend if4
|
| #
61de3d93 |
| 08-Jan-2021 |
Lingrui98 <[email protected]> |
Merge remote-tracking branch 'origin/ifu-timing' into ifu-pakcet-aligned
|
| #
4244727e |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
predecode: fix typo
|
| #
c1be9e58 |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
predecode: fix a bug of not assigning width for pc generation
|
| #
8e32e436 |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
icache, predecode, loopbuffer: fix compiling errors
|
| #
2b32f7df |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
ifu: code clean ups
|
| #
576af497 |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
ifu, bpu: totally remove the concept of 'bank'
|
| #
a6a1f5ed |
| 07-Jan-2021 |
Lingrui98 <[email protected]> |
predecode: fix a bug on has rvc of lastIsValidEnd
|
| #
cfcf47ee |
| 04-Jan-2021 |
Lingrui98 <[email protected]> |
frontend: use HasCExtension to control whether we support rvc
|
| #
a1cf420c |
| 12-Dec-2020 |
Zhangfw <[email protected]> |
PreDecode: fixed RVC mask
|
| #
57c3c8de |
| 10-Dec-2020 |
Lingrui98 <[email protected]> |
predecode: fix a bug on last half RVI
|
| #
04fb04ef |
| 03-Dec-2020 |
Lingrui98 <[email protected]> |
ifu, bpu, predecode: several bugs fixed, now we can run coremark at a low performance
|
| #
ceaf5e1f |
| 01-Dec-2020 |
Lingrui98 <[email protected]> |
frontend: half done refactoring
|
| #
cc6108c7 |
| 29-Nov-2020 |
Lingrui98 <[email protected]> |
predecode: simplify logic and take loopbuffer into account
THIS COMMIT DOES NOT WORK!
|
| #
13953c61 |
| 29-Nov-2020 |
Lingrui98 <[email protected]> |
predecode: modify logic to fit the new semantic of inMask
THIS COMMIT DOES NOT WORK!!
|
| #
25114934 |
| 05-Nov-2020 |
Lingrui98 <[email protected]> |
predecode: totally fix isCall logic for both rvc and non-rvc instructions
|
| #
b152d0c3 |
| 04-Nov-2020 |
Lingrui98 <[email protected]> |
predecode: fix a bug which identify c.j as call
|
| #
84456065 |
| 18-Aug-2020 |
jinyue110 <[email protected]> |
PreDecoder: change signal into IcacheResp
|
| #
871474f6 |
| 10-Aug-2020 |
zhangfw <[email protected]> |
predecode:fixed ret type
|
| #
36cbebc4 |
| 10-Aug-2020 |
zhangfw <[email protected]> |
predeocde:fix ret type
|
| #
0711c1d2 |
| 10-Aug-2020 |
zhangfw <[email protected]> |
predecode:fix ret type
|
| #
12dcbb5b |
| 10-Aug-2020 |
zhangfw <[email protected]> |
predecode: fixed ret type(mbpright 63629->66373)
|
| #
c8cc6402 |
| 06-Aug-2020 |
zhanglinjuan <[email protected]> |
ifu: add c.j target-gen logic
predecode: fix bug in isCall and isRet
micorbench and coremark pass!
|
| #
e9199ec7 |
| 06-Aug-2020 |
zhanglinjuan <[email protected]> |
ifu/bpu: fix bug in saveHalfRVI
|