ftq: prefetch read address from pc_mem

* add diff for upate_target and pc_mem result

ftq: fix compiling errors

ftq: use previous update_target as difftest

ftq: remove update_target regs and use next entry start as target

ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles

ftq: add predecode redirect update target interface, valid only on ifuRedirect

ftq, icache: fix compilation errors

ftq: copy bpu bypass write registers

* FtqToICache add bypass write signal and use bypass signal

IFU/IPrefetch/ReplacePipe: adjust meta/data access

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a co

IFU/IPrefetch/ReplacePipe: adjust meta/data access

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a copied register trigger by FTQ
requests

* IPrefetch/ReplacePipe: expand meta/data access outpu to 4 indentical
vector output, and each output is triggered by the same signal group

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[WIP]FTQ: add icache req port

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]FTQ: add icache req port

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]ICacheMainPipe: add copied registers

[WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied

[WIP] FTQ: delete outside bypass

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ftq,ctrl: add copies for pc and jalr_target data modules (#1661)

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

Thi

ftq,ctrl: add copies for pc and jalr_target data modules (#1661)

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

This commit adds two data modules for pc and jalr_target respectively.
They are the same as data modules in frontend. Should benefit timing.

* jump: reduce pc and jalr_target read latency

* ftq: add predecode redirect update target interface, valid only on ifuRedirect

* ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles

Co-authored-by: Lingrui98 <[email protected]>

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datamodule: add per-read-port bypass enable bit (#1635)

and remove all bypass for ftq_pc_mem

frontend: Add ChiselDB records

IFU: Add toIBuffer and toFtq record
Ftq: Add branch trace datebase framework

ftq,ctrl: add copies for pc and jalr_target data modules (#1661)

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

ftq,ctrl: add copies for pc and jalr_target data modules (#1661)

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

This commit adds two data modules for pc and jalr_target respectively.
They are the same as data modules in frontend. Should benefit timing.

* jump: reduce pc and jalr_target read latency

* ftq: add predecode redirect update target interface, valid only on ifuRedirect

* ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles

Co-authored-by: Lingrui98 <[email protected]>

show more ...

bpu, ftb, ftq: timing optimizations

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

ftq: keep track of next ifuPtr using a register

ftq: add one cycle delay to write status registers, and add more bypass logic for entry_fetch_status

Merge pull request #1574 from OpenXiangShan/fix-ifu-ready

<bug-fix>: fix IFU misOffset bug and optimize code

ftq: should use jmpOffset instead of cfiIndex when assigning (#1561)

last_may_be_rvi_call in case that a call comes after a taken branch

discard iprefetch req when resource busy

fix for chipsalliance/chisel3#2496 (#1563)

Bump chisel to 3.5.0

ctrl,ftq: move pc and target calculation in redirect generator to ftq (#1463)

ftq: read entry fetch status one cycle ahead (#1450)

ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address