Frontend: add RVC illegal instruction buffer

* Sstval requires instructions to be filled into stval

svpbmt: add simplified support (#3404)

Only the `pbmt` attribute is added and treated as MMIO when `pbmt` is NC
or IO.

---------

Co-authored-by: ngc7331 <[email protected]>

IFU: fix cross-page exception (#3386)

See https://github.com/OpenXiangShan/XiangShan/pull/3354#discussion_r1718219297

Cross-page access faults are not marked (in the past 2-3 years), so this
PR

IFU: fix cross-page exception (#3386)

See https://github.com/OpenXiangShan/XiangShan/pull/3354#discussion_r1718219297

Cross-page access faults are not marked (in the past 2-3 years), so this
PR fixed that too.

Also, `crossPageIPFFix` (actually `crossPageExceptionFix`, used to
calculate precise exception address in CSR) should be set for both
pf/gpf/af (and mmio_resend pf/gpf/af).

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Frontend: refactor exceptions to labels (#3354)

Combine `excp_pf`/`_gpf`/`_af` into `exception` to:
1. Reduce code redundancy and improve readability and maintainability
e.g. `!itlb_excp_af && !it

Frontend: refactor exceptions to labels (#3354)

Combine `excp_pf`/`_gpf`/`_af` into `exception` to:
1. Reduce code redundancy and improve readability and maintainability
e.g. `!itlb_excp_af && !itlb_excp_pf && !itlb_excp_gpf && !pmp_excp_af
&& !pmp_excp_mmio`
-> `exception === ExcedptionType.none && !mmio`
2. Select exceptions as they are generated (e.g. from iTLB/PMP, or
data/meta array ECC check) on a priority basis (e.g. iTLB over PMP),
ensuring that there is at most one exception in the pipeline (and on the
ports of iCache -> IFU)
3. Save a little bit of pipeline/WayLookup registers (i.e. 3 bit
`excp_pf`/`_gpf`/`_af` -> 2bit `exception`)

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IFU: fix mmio fsm for itlb handshake (#3329)

Fixes state transfer condition of `m_sendTLB` and `m_tlbResp` in IFU
mmio fsm.

https://github.com/OpenXiangShan/XiangShan/blob/091c28ff02749943c410f4

IFU: fix mmio fsm for itlb handshake (#3329)

Fixes state transfer condition of `m_sendTLB` and `m_tlbResp` in IFU
mmio fsm.

https://github.com/OpenXiangShan/XiangShan/blob/091c28ff02749943c410f414784d991bc205e8cb/src/main/scala/xiangshan/frontend/IFU.scala#L659-L663

## Story
2 years ago, TLB can be configured as `sameCycle` and therefore
`io.iTLBInter.resp.bits.miss` is in the same cycle with
`io.iTLBInter.req.fire`, see:
https://github.com/OpenXiangShan/XiangShan/blob/c3b2d83a43a64198f94aced1db4b998ebf29a3bb/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala#L59-L62

In that case, the current fsm will wait in state `m_sendTLB` until
`io.iTLBInter.resp.bits.miss === false.B` (TLB hit or PTW work done),
and enters state `m_tlbResp` in next cycle, getting the correct response
(`paddr`, etc.).

However, currently `io.iTLBInter.resp.bits.miss` is returned 1 cycle
after `io.iTLBInter.req.fire`, see:

https://github.com/OpenXiangShan/XiangShan/blob/091c28ff02749943c410f414784d991bc205e8cb/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala#L125-L130

And the IFU mmio fsm is unchanged, it may use the `miss` from last TLB
request, make real `miss` ignored and send invalid `paddr` to Uncache.

## Solution
1. Send `io.iTLBInter.req.valid` in state `m_sendTLB` as before, just
wait `io.iTLBInter.req.fire` to enter state `m_tlbResp`.
2. Wait `io.iTLBInter.resp.valid` in state `m_tlbResp` (in blocked TLB,
this also indicates `io.iTLBInter.resp.bits.miss === false.B`), get
valid response and enter next state.

Also:
Close #2658

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LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need t

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need to do pmp check, so we also need to send signal of `no_translate`.

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build: purge chisel 3 and add deprecation check (#3250)

IFU: remove duplicate assignment for f3_ready (#3138)

f3_ready is assigned twice under the identical condition:
-
https://github.com/OpenXiangShan/XiangShan/blob/182b7ece8ba898233f30d6cd83bbed5082

IFU: remove duplicate assignment for f3_ready (#3138)

f3_ready is assigned twice under the identical condition:
-
https://github.com/OpenXiangShan/XiangShan/blob/182b7ece8ba898233f30d6cd83bbed50825943de/src/main/scala/xiangshan/frontend/IFU.scala\#L471
-
https://github.com/OpenXiangShan/XiangShan/blob/182b7ece8ba898233f30d6cd83bbed50825943de/src/main/scala/xiangshan/frontend/IFU.scala\#L585

and the former one:
```scala
f3_ready := f3_fire || !f3_valid
// := (io.toIbuffer.ready && f3_valid && (!f3_req_is_mmio || f3_mmio_can_go) && !f3_flush) || !f3_valid
```
might not ideal since the previous mmio request may be not commited
(i.e. `mmio_state === m_waitCommit`)

therefore, remove the former assignment

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IFU: pass mmio gpf to ibuffer & gpaddr to gpaMem (#3182)

also reset `mmio_resend_(a|p|gp)f` registers when mmio instr is commited
or flush happens

Frontend: cut waylookup gpaddr (#3139)

Currently, `gpaddr` is used only when guest page fault occurs, so it
should be possible to not store every `gpaddr` in WayLookup (as well as
in GPAMem).

C

Frontend: cut waylookup gpaddr (#3139)

Currently, `gpaddr` is used only when guest page fault occurs, so it
should be possible to not store every `gpaddr` in WayLookup (as well as
in GPAMem).

Considering that every guest page fault should issue a redirect, and
thus flush WayLookup/MainPipe/IPrefetch, we should be able to store only
the first guest page fault and its `gpaddr` in WayLookup.

By doing this, we can save `2×nWayLookupSize - 1 = 63` registers that
are used to store `gpaddr`.

This PR also includes some style changes for WayLookup to satisfy
linter.

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IFU: cut the number of PC registers (#3103)

In order to reduce power consumption, some unnecessary PC registers can
be trimmed.

---------

Co-authored-by: zhou tao <[email protected]

IFU: cut the number of PC registers (#3103)

In order to reduce power consumption, some unnecessary PC registers can
be trimmed.

---------

Co-authored-by: zhou tao <[email protected]>

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build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118)

refactor: change exception encoding from one-hot to label (#3104)

ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

IFU: fix the bug of postponing MMIO instruction fetch strategy (#3038)

Co-authored-by: zhou tao <[email protected]>

IFU,ICache: clock gating optimization (#2957)


Co-authored-by: Liang Sen <[email protected]>

IFU & GPAMem, RVH: fix the bug about getting gpa (#2960)

1. Delete some useless codes about gpaddr.
2. fix the bugs about wrong gpa was writen in mtval2 or htval when guest
page fault occured

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

frontend: add a gpaddr write data path

add a data path in Ifu, which write gpaddr to backend at the same time
as write to IBuffer

Merge remote-tracking branch 'upstream/master' into tmp-master

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

Ibuffer, PreDecode: consider valids for assertions (#2871)

RVH: fix the errors after git rebase

RVH: fix a bug that gpaddr error in icache

RVH: update H-ext design with master