BPU: add clock gating (#2733)

Co-authored-by: Liang Sen <[email protected]>

Revert sram split (#2518)

* Revert "ICache: split dataArray from 4*128x1024 to 16*128x256 for physical synthesis (#2493)"

This reverts commit 787ba0d9994ae9ffb3a7ea036d6d8341b3b4aa4d.

* Revert

Revert sram split (#2518)

* Revert "ICache: split dataArray from 4*128x1024 to 16*128x256 for physical synthesis (#2493)"

This reverts commit 787ba0d9994ae9ffb3a7ea036d6d8341b3b4aa4d.

* Revert "bpu: change FTB SRAM width (#2497)"

This reverts commit 6955909f77f3b672e0111bb46bf068b86615435b.

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bpu: change FTB SRAM width (#2497)

top-down: move sc from ftb to redirect sram (#2397)

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

New RAS design (#2292)

By introducing non-volatile queue for specutive states, RAS avoids entry pollution

Co-authored-by: Easton Man <[email protected]>

FTB(timing): fix s2 target & fallthrough address (#2273)

* FTB(timing): use s1_pc in target calculation

* FTB(timing): use last_stage_entry.carry in fallthrough address Mux()

FTB(timing): delay replacer update on read (#2227)

* FTB: postpone read replacer access

this helps with timing

* FTB: add comments about replace logic

bpu: duplicate most possible signal related to npc generation to address (#2254)

high fanout problems

Co-authored-by: Lingrui98 <[email protected]>

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

bpu: remove minimal pred and old ubtb

bpu: add reset back

bpu: refactor prediction i/o bundles

bpu: remove most reset signals of SRAMs

bpu, ftb, ftq: timing optimizations

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

ftb: update replacer state when update request is sent from ftq

bpu, ftb, ftq: timing optimizations

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

ftb: update replacer state when update request is sent from ftq (#1479)

bpu: bring bpu control signals into use (#1477)

ftb: fix a bug on replacement policy, remove multiple hit assert (#1455)

the mulitple-hit problem is yet to be solved (although it may be very rare)

ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

bpu,ftq: remove oversize logic

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer

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