refactor(DFT): refactor `DFT` IO (#4530)

fix(FTB, FTQ): dont use CPL2 SplittedSRAM (#4485)

If the frontend directly uses the SplittedSRAM of coupledL2, the
frontend's SRAM will be marked as a multi-cycle path, the same as
coupledL2's SRAM.

feat(FTB, FTQ): split FTB meta SRAM and FTQ meta SRAM (#4360)

FTB meta SRAM: 512 × 320 -> (512 × 40) × 8
FTQ meta SRAM: 64 × 320 -> (64 × 160) × 2

chore: fix several deprecation warning (#4352)

feat(dfx): integerate dfx components (#4312)

power(bpu): optimize CGE of bpu/predictors_io_update (#3579)

Bpu: Optimize CGE of bpu/predictors_io_update by moving update regs into
predictors, except for the update PC

---------

Co-authore

power(bpu): optimize CGE of bpu/predictors_io_update (#3579)

Bpu: Optimize CGE of bpu/predictors_io_update by moving update regs into
predictors, except for the update PC

---------

Co-authored-by: pengxiao <[email protected]>

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feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\)

feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\) to ensure single-port SRAM access.
* when SRAM is multi-port, the read and write ports of the multi-port
SRAM are gated using different clocks.

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feat(ftb): add ftb tag length param (#3855)

fix(ftb): fix ftb pred_rdata not reset (#3628)

feat(ittage): Reuse always_taken to mark the first occurrence of the jalr inst (#3718)

Reuse always_taken to mark the first occurrence of the jalr instruction
and rename always_taken to strong_bias.

feat(ftb): add fallThroughErr check function to check FTBEntry given by S3 level (#3794)

The FTBEntry given by s3 level in the design expectation should not have
a fallThroughErr of true.

fix(FTB): Turn off FTB updates when FTB is closed. (#3543)

During the shutdown period of FTB, there is no need to make FTB update
requests, which has performance benefits for FTQ blocking caused by

fix(FTB): Turn off FTB updates when FTB is closed. (#3543)

During the shutdown period of FTB, there is no need to make FTB update
requests, which has performance benefits for FTQ blocking caused by FTB
updates after FTB shutdown

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style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

fix(ftb): When FTB is closed, the s2_multi_hit_enable should be lowered & Add FTB reading port low fallthroughErr assert (#3641)

feat(btb): add index hash (#3563)

this avoids btb conflict in some special pattern

fix(BPU): adjust s3 target when fallThroughErr signal is high (#3636)

1. adjust S3 target address selection.

fix(BPU): adjust fallThroughErr signal usage strategy (#3627)

fix(ftb,uftb): Fallthrough address comparison canceled during prediction (#3630)

fix(BPU): modify the usage of the fallThroughErr signal (#3610)

bpu: use (27, 12, 12) segmented PC in BPU (#3027)

In dhrystone, most high bits of PC is gated.

bpu: disable ittage when no indirect branch & ittage backward shift (#3092)

Co-authored-by: Easton Man <[email protected]>

ftb: Higher register splitting for clock gating efficiency(#2981)

FTB: Merge ftb low power & fix fallThroughAddr calculation. (#2997)

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: sc

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: scMeta-tageTakens/scUsed/providerResps-unconf/altDiffers/takens;
dlt ITTage: altDiffers/taken
dlt uFTB: pred_way
dlt RAS: sctr/TOSR/NOS

ftq_redirect_sram->ftq_redirect_mem

Co-authored-by: chenguokai <[email protected]>

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