ubtb: alloc ways on write

Merge branch 'master' into bpu-perf

perf: Modify perf counters logic

perf: Add perf counters for predictors

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and sbpctl address

* bpu: fix s3 connections

Co-authored-by: Yinan Xu <[email protected]>

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Merge branch 'ftq-loop' into dev-sc

Merge branch 'master' into ftq-loop

LoopPredictor: Modify the loop predictor to adapt to ftq

sc: fit sc to current version

bundle: some signals should only exist when enable debug

ibuffer: remove pnpc
ifu: reconsider prediction of prevHalfInstr
now we do not need to gather meta from the last packet
because we update with packet, thus updating in the
correct slot

bpu: repair ras top when redirect

RAS: add EnableCommit option

when enable commit, RAS use commit stack to recover,else we use CFI
update info to recover RAS sp and top register.

bpu: update commit log

ifu: add br target calculation

ftq and all: now we can compile

bpu: remove flush signals

ifu: code clean ups

ifu, bpu: totally remove the concept of 'bank'

bpu: remove useless comments

bpu: wrap fire io into a trait

bpu: fix compile error

Merge branch 'ifu-timing' of https://github.com/RISCVERS/XiangShan into ifu-timing

bpu: add fire signals as default io

Merge branch 'ifu-timing' into timing-loop