issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
cafb3558	11-Jul-2020	LinJiawei <[email protected]>	Refactor exu /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/XSTrap.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVM.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/utils/PriorityMuxDefault.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
8557b6ec	11-Jul-2020	Yinan Xu <[email protected]>	dispatch,iq: add numExists to give RS priority /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/src/main/scala/bus/simplebus/DistributedMem.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala
faf96e75	10-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: optimization of enq'deq with no delay with fifo IssueQueue.scala
83359ba6	10-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of enq with no delay when fifo IssueQueue.scala
e629f141	10-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: optimization, enq may issue with no delay(two stage) Optimization: when the terms in issueQueue have no rdy && enq is rdy && first stage is empty then send the enq term directly /XiangShan/.github/workflows/core_ci.yml /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/XSTrap.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
09b6ad0b	09-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of srcType check when enq IssueQueue.scala
54189f6d	09-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: IQ now output numExist signal to Dispatch /XiangShan/src/main/scala/xiangshan/XSCore.scala IssueQueue.scala
7a6fb177	09-Jul-2020	ZhangZifei <[email protected]>	Merge branch 'master' into issueQueue-compact /XiangShan/Makefile /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/utils/PriorityMuxDefault.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
53da9409	06-Jul-2020	Yinan Xu <[email protected]>	dispatch2,issuequeue: bug fix /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Mul.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
bfa4b2b4	04-Jul-2020	LinJiawei <[email protected]>	Cmp brTag /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/utils/LogUtils.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
ebfa1e8e	04-Jul-2020	LinJiawei <[email protected]>	Add log info /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
1c59c471	03-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: change "for"'s code for Paramterization and beauty IssueQueue.scala
bda49d31	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of overwrite of validQue/IssueToFireValid /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/utils/MIMOQueue.scala /XiangShan/src/test/csrc/emu.h
dbb15897	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: remove some log of srcDataWire IssueQueue.scala
5753cbdf	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: support in-order issueQueue. fix bug: enq/deq mix ptr also rename enqSel to enqSelIq IssueQueue.scala
73747960	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: remove old IssueQueue module. and rename IssueQueueCpt to IssueQueue /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala
d569aaf1	02-Jul-2020	ZhangZifei <[email protected]>	Merge remote-tracking branch 'origin/master' into issueQueue-compact /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
8b84f603	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of srcDataWire IssueQueue.scala
2d3721b3	02-Jul-2020	LinJiawei <[email protected]>	IssueQueue: fix 'i' bug to 'j' /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
997a8549	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of src2Listen/src3Listen also remove some commented code IssueQueue.scala
415607b1	02-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of srcUse/srcListen IssueQueue.scala
16a9b60c	01-Jul-2020	ZhangZifei <[email protected]>	Merge branch 'master' into issueQueue-compact add IssueQueueCpt(IssueQueueCompact) /XiangShan/.gitignore /XiangShan/build.sc /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Bru.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Lsu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeIFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala
b9bb7e73	01-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: add some assert and change some log IssueQueue.scala
19113dc3	01-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of enqRedirect and id's writeback when pop IssueQueue.scala
01753476	01-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: fix bug of deqSel's mix between IDque's idx and IQue's IssueQueue.scala
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