1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14} 15 16// Dequeue DecodeWidth insts from Ibuffer 17class CtrlFlow extends XSBundle { 18 val instr = UInt(32.W) 19 val pc = UInt(VAddrBits.W) 20 val exceptionVec = Vec(16, Bool()) 21 val intrVec = Vec(12, Bool()) 22 val isRVC = Bool() 23 val isBr = Bool() 24} 25 26// Decode DecodeWidth insts at Decode Stage 27class CtrlSignals extends XSBundle { 28 val src1Type, src2Type, src3Type = SrcType() 29 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 30 val ldest = UInt(5.W) 31 val fuType = FuType() 32 val fuOpType = FuOpType() 33 val rfWen = Bool() 34 val fpWen = Bool() 35 val isXSTrap = Bool() 36 val noSpecExec = Bool() // This inst can not be speculated 37 val isBlocked = Bool() // This inst requires pipeline to be blocked 38 val isRVF = Bool() 39 val imm = UInt(XLEN.W) 40} 41 42class CfCtrl extends XSBundle { 43 val cf = new CtrlFlow 44 val ctrl = new CtrlSignals 45 val brTag = new BrqPtr 46} 47 48// CfCtrl -> MicroOp at Rename Stage 49class MicroOp extends CfCtrl { 50 51 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 52 val src1State, src2State, src3State = SrcState() 53 val freelistAllocPtr = new FreeListPtr 54 val roqIdx = UInt(RoqIdxWidth.W) 55} 56 57class Redirect extends XSBundle { 58 val target = UInt(VAddrBits.W) 59 val brTag = new BrqPtr 60 val isException = Bool() 61 val roqIdx = UInt(RoqIdxWidth.W) 62 val freelistAllocPtr = new FreeListPtr 63} 64 65class RedirectInfo extends XSBundle { 66 67 val valid = Bool() // a valid commit form brq/roq 68 val misPred = Bool() // a branch miss prediction ? 69 val redirect = new Redirect 70 71 def flush():Bool = valid && (redirect.isException || misPred) 72} 73 74class Dp1ToDp2IO extends XSBundle { 75 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 76 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 77 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 78} 79 80class DebugBundle extends XSBundle{ 81 val isMMIO = Bool() 82} 83 84class ExuInput extends XSBundle { 85 val uop = new MicroOp 86 val src1, src2, src3 = UInt(XLEN.W) 87} 88 89class ExuOutput extends XSBundle { 90 val uop = new MicroOp 91 val data = UInt(XLEN.W) 92 val redirectValid = Bool() 93 val redirect = new Redirect 94 val debug = new DebugBundle 95} 96 97class ExuIO extends XSBundle { 98 val in = Flipped(DecoupledIO(new ExuInput)) 99 val redirect = Flipped(ValidIO(new Redirect)) 100 val out = DecoupledIO(new ExuOutput) 101 102 // for Lsu 103 val dmem = new SimpleBusUC 104 val scommit = Input(UInt(3.W)) 105} 106 107class RoqCommit extends XSBundle { 108 val uop = new MicroOp 109 val isWalk = Bool() 110} 111 112class FrontendToBackendIO extends XSBundle { 113 // to backend end 114 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 115 // from backend 116 val redirectInfo = Input(new RedirectInfo) 117 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 118} 119