rv64v: fix mask control for vector compare instructions (#3202)

ci: add simple xprop test through vcs (#3071)

FU: fix mgu for body elements's agnostic

* Modify the signal names about divided vector elements to be consistent with RVV Spec.

(cherry picked from commit 81cbff077dfbdc9bccc3bcfb47d9666617c23f0e)

VldMergeUnit, Mgu: add VldMgu

rv64v: fix vxsat and vd compute for fixed-point instruction

Mgu: fix element width that each bit in mask stands for

For vector indexed loads/stores, data width equals sew instead of
eew. So each one bit stands for sew-width data in vmask.

Mgu: use sew as element width instead of eew for indexed loads/stores

Mgu: move activeEn and tailEn into ByteMaskTailGen without truncating
vstart and vl

vector: convert mgu's assertion to EX_II

fix merge errors

fix merge error

assert: mgu's vl must <= vlmax

fix: use mask to generate the vxsat

modify the fix-point vector alu wrapper and mgu

vector: fix Mgu error

* Width of vlMapVdIdx should be 4-bit, because vl can equal to VLEN. In this case, vlMapVdIdx is 8.

vector: update Mgu

vector: move Mgu