xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala (revision 92c6b7ed48080c3cce748a3ba908d80c1e288689) 
1/****************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ****************************************************************************************
16 */
17
18
19package xiangshan.backend.fu.vector
20
21import org.chipsalliance.cde.config.Parameters
22import chisel3._
23import chisel3.util._
24import chiseltest._
25import chiseltest.ChiselScalatestTester
26import org.scalatest.flatspec.AnyFlatSpec
27import org.scalatest.matchers.must.Matchers
28import top.{ArgParser, BaseConfig, DefaultConfig}
29import xiangshan._
30import xiangshan.backend.fu.vector.Bundles.{VSew, Vl}
31import xiangshan.backend.fu.vector.Utils.VecDataToMaskDataVec
32import yunsuan.vector._
33
34class Mgu(vlen: Int)(implicit p: Parameters) extends  Module {
35  private val numBytes = vlen / 8
36  private val byteWidth = log2Up(numBytes)
37
38  val io = IO(new MguIO(vlen))
39
40  val in = io.in
41  val out = io.out
42  val info = in.info
43  val vd = in.vd
44  val oldVd = in.oldVd
45  val narrow = io.in.info.narrow
46
47  private val vdIdx = Mux(narrow, info.vdIdx(2, 1), info.vdIdx)
48
49  private val maskTailGen = Module(new ByteMaskTailGen(vlen))
50
51  private val eewOH = SewOH(info.eew).oneHot
52
53  private val vstartMapVdIdx = elemIdxMapVdIdx(info.vstart)(2, 0) // 3bits 0~7
54  private val vlMapVdIdx = elemIdxMapVdIdx(info.vl)(3, 0)         // 4bits 0~8
55  private val uvlMax = numBytes.U >> info.eew
56  private val uvlMaxForAssert = numBytes.U >> info.vsew
57  private val vlMaxForAssert = Mux(io.in.info.vlmul(2), uvlMaxForAssert >> (-io.in.info.vlmul), uvlMaxForAssert << io.in.info.vlmul).asUInt
58
59  private val maskDataVec: Vec[UInt] = VecDataToMaskDataVec(in.mask, info.eew)
60  private val maskUsed = maskDataVec(vdIdx)
61
62  private val realEw = Mux(in.isIndexedVls, info.vsew, info.eew)
63
64  maskTailGen.io.in.begin := info.vstart /*Mux1H(Seq(
65    (vstartMapVdIdx < vdIdx) -> 0.U,
66    (vstartMapVdIdx === vdIdx) -> elemIdxMapUElemIdx(info.vstart),
67    (vstartMapVdIdx > vdIdx) -> uvlMax,
68  ))*/
69  maskTailGen.io.in.end := info.vl /*Mux1H(Seq(
70    (vlMapVdIdx < vdIdx) -> 0.U,
71    (vlMapVdIdx === vdIdx) -> elemIdxMapUElemIdx(info.vl),
72    (vlMapVdIdx > vdIdx) -> uvlMax,
73  ))*/
74  maskTailGen.io.in.vma := info.ma
75  maskTailGen.io.in.vta := info.ta
76  maskTailGen.io.in.vsew := realEw
77  maskTailGen.io.in.maskUsed := maskUsed
78  maskTailGen.io.in.vdIdx := info.vdIdx
79
80  private val keepEn = maskTailGen.io.out.keepEn
81  private val agnosticEn = maskTailGen.io.out.agnosticEn
82
83  // the result of normal inst and narrow inst which does not need concat
84  private val byte1s: UInt = (~0.U(8.W)).asUInt
85
86  private val resVecByte = Wire(Vec(numBytes, UInt(8.W)))
87  private val vdVecByte = vd.asTypeOf(resVecByte)
88  private val oldVdVecByte = oldVd.asTypeOf(resVecByte)
89
90  for (i <- 0 until numBytes) {
91    resVecByte(i) := MuxCase(oldVdVecByte(i), Seq(
92      keepEn(i) -> vdVecByte(i),
93      agnosticEn(i) -> byte1s,
94    ))
95  }
96
97  // the result of narrow inst which needs concat
98  private val narrowNeedCat = info.vdIdx(0).asBool & narrow
99  private val narrowResCat = Cat(resVecByte.asUInt(vlen / 2 - 1, 0), oldVd(vlen / 2 - 1, 0))
100
101  // the result of mask-generating inst
102  private val maxVdIdx = 8
103  private val meaningfulBitsSeq = Seq(16, 8, 4, 2)
104  private val allPossibleResBit = Wire(Vec(4, Vec(maxVdIdx, UInt(vlen.W))))
105  private val catData = Mux(info.ta, ~0.U(vlen.W), oldVd)
106
107  for (sew <- 0 to 3) {
108    if (sew == 0) {
109      allPossibleResBit(sew)(maxVdIdx - 1) := Cat(vd(meaningfulBitsSeq(sew) - 1, 0),
110        oldVd(meaningfulBitsSeq(sew) * (maxVdIdx - 1) - 1, 0))
111    } else {
112      allPossibleResBit(sew)(maxVdIdx - 1) := Cat(catData(vlen - 1, meaningfulBitsSeq(sew) * maxVdIdx),
113        vd(meaningfulBitsSeq(sew) - 1, 0), oldVd(meaningfulBitsSeq(sew) * (maxVdIdx - 1) - 1, 0))
114    }
115    for (i <- 1 until maxVdIdx - 1) {
116      allPossibleResBit(sew)(i) := Cat(catData(vlen - 1, meaningfulBitsSeq(sew) * (i + 1)),
117        vd(meaningfulBitsSeq(sew) - 1, 0), oldVd(meaningfulBitsSeq(sew) * i - 1, 0))
118    }
119    allPossibleResBit(sew)(0) := Cat(catData(vlen - 1, meaningfulBitsSeq(sew)), vd(meaningfulBitsSeq(sew) - 1, 0))
120  }
121
122  private val resVecBit = allPossibleResBit(info.eew)(vdIdx)
123
124  io.out.vd := MuxCase(resVecByte.asUInt, Seq(
125    info.dstMask -> resVecBit.asUInt,
126    narrowNeedCat -> narrowResCat,
127  ))
128  io.out.keep := keepEn
129  io.out.illegal := (info.vl > vlMaxForAssert) && info.valid
130
131  io.debugOnly.vstartMapVdIdx := vstartMapVdIdx
132  io.debugOnly.vlMapVdIdx := vlMapVdIdx
133  io.debugOnly.begin := maskTailGen.io.in.begin
134  io.debugOnly.end := maskTailGen.io.in.end
135  io.debugOnly.keepEn := keepEn
136  io.debugOnly.agnosticEn := agnosticEn
137  def elemIdxMapVdIdx(elemIdx: UInt) = {
138    require(elemIdx.getWidth >= log2Up(vlen))
139    // 3 = log2(8)
140    Mux1H(eewOH, Seq.tabulate(eewOH.getWidth)(x => elemIdx(byteWidth - x + 3, byteWidth - x)))
141  }
142
143  def elemIdxMapUElemIdx(elemIdx: UInt) = {
144    Mux1H(eewOH, Seq.tabulate(eewOH.getWidth)(x => elemIdx(byteWidth - x - 1, 0)))
145  }
146}
147
148
149class MguIO(vlen: Int)(implicit p: Parameters) extends Bundle {
150  val in = new Bundle {
151    val vd = Input(UInt(vlen.W))
152    val oldVd = Input(UInt(vlen.W))
153    val mask = Input(UInt(vlen.W))
154    val info = Input(new VecInfo)
155    val isIndexedVls = Input(Bool())
156  }
157  val out = new Bundle {
158    val vd = Output(UInt(vlen.W))
159    val keep = Output(UInt((vlen / 8).W))
160    val illegal = Output(Bool())
161  }
162  val debugOnly = Output(new Bundle {
163    val vstartMapVdIdx = UInt()
164    val vlMapVdIdx = UInt()
165    val begin = UInt()
166    val end = UInt()
167    val keepEn = UInt()
168    val agnosticEn = UInt()
169  })
170}
171
172class VecInfo(implicit p: Parameters) extends Bundle {
173  val ta = Bool()
174  val ma = Bool()
175  val vl = Vl()
176  val vstart = Vl()
177  val eew = VSew()
178  val vsew = VSew()
179  val vdIdx = UInt(3.W) // 0~7
180  val vlmul = UInt(3.W)
181  val valid = Bool()
182  val narrow = Bool()
183  val dstMask = Bool()
184}
185
186object VerilogMgu extends App {
187  println("Generating the Mgu hardware")
188  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
189  val p = config.alterPartial({case XSCoreParamsKey => config(XSTileKey).head})
190
191  emitVerilog(new Mgu(128)(p), Array("--target-dir", "build/vifu", "--full-stacktrace"))
192}
193
194class MguTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
195
196  val defaultConfig = (new DefaultConfig).alterPartial({
197    case XSCoreParamsKey => XSCoreParameters()
198  })
199
200  println("test start")
201
202  behavior of "Mgu"
203  it should "run" in {
204    test(new Mgu(128)(defaultConfig)).withAnnotations(Seq(VerilatorBackendAnnotation)) {
205      m: Mgu =>
206        m.io.in.vd.poke("h8765_4321_8765_4321_8765_4321_8765_4321".U)
207        m.io.in.oldVd.poke("h7777_7777_7777_7777_7777_7777_7777_7777".U)
208        m.io.in.mask.poke("h0000_0000_0000_0000_0000_0000_ffff_0000".U)
209        m.io.in.info.ta.poke(true.B)
210        m.io.in.info.ma.poke(false.B)
211        m.io.in.info.vl.poke((16 + 7).U)
212        m.io.in.info.vstart.poke((16 + 2).U)
213        m.io.in.info.eew.poke(VSew.e8)
214        m.io.in.info.vdIdx.poke(1.U)
215
216        println("out.vd: " + m.io.out.vd.peek().litValue.toString(16))
217        println("debugOnly.vstartMapVdIdx: " + m.io.debugOnly.vstartMapVdIdx.peek().litValue.toString(16))
218        println("debugOnly.vlMapVdIdx: "     + m.io.debugOnly.vlMapVdIdx.peek().litValue.toString(16))
219        println("debugOnly.begin: "          + m.io.debugOnly.begin.peek().litValue)
220        println("debugOnly.end: "            + m.io.debugOnly.end.peek().litValue)
221        println("debugOnly.keepEn: "         + m.io.debugOnly.keepEn.peek().litValue.toString(2))
222        println("debugOnly.agnosticEn: "     + m.io.debugOnly.agnosticEn.peek().litValue.toString(2))
223    }
224    println("test done")
225  }
226}