xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala (revision ff38b6c75ebf2ab4ca9f9ac562044f157e3b492a) 
1/****************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ****************************************************************************************
16 */
17
18
19package xiangshan.backend.fu.vector
20
21import chisel3._
22import chisel3.util._
23import yunsuan.vector._
24
25class Mgu extends  Module {
26  val io = IO(new MguIO)
27
28  val in = io.in
29  val out = io.out
30  val info = in.info
31
32  val eewOH = SewOH(info.eew)
33  val tail = TailGen(info.vl, info.uopIdx, eewOH, false.B)
34  val prestart = PrestartGen(info.vstart, info.uopIdx, eewOH, false.B)
35  val mask = MaskExtract(in.mask, info.uopIdx, eewOH)
36  val vstart_gte_vl = info.vstart >= info.vl
37  val tailReorg = MaskReorg.splash(tail, eewOH)
38  val prestartReorg = MaskReorg.splash(prestart, eewOH)
39  val maskReorg = MaskReorg.splash(mask, eewOH)
40  val updateType = Wire(Vec(16, UInt(2.W))) // 00: keep result  10: old_vd  11: write 1s
41  for(i <- 0 until 16) {
42    when(prestartReorg(i) || vstart_gte_vl) {
43      updateType(i) := 2.U
44    }.elsewhen(tailReorg(i)) {
45      updateType(i) := Mux(info.ta, 3.U, 2.U)
46    }.elsewhen(!info.vm && !maskReorg(i)) {
47      updateType(i) := Mux(info.ma, 3.U, 2.U)
48    }.otherwise {
49      updateType(i) := 0.U
50    }
51  }
52  val bitsKeep = Cat(updateType.map(x => Mux(x(1), 0.U(8.W), ~0.U(8.W))).reverse)
53  val bitsReplace = Cat(updateType.zipWithIndex.map({ case (x, i) =>
54    Mux(!x(1), 0.U(8.W), Mux(x(0), ~0.U(8.W), UIntSplit(in.old_src, 8)(i)))
55  }).reverse)
56
57
58  out.vd := in.src & bitsKeep | bitsReplace
59
60}
61
62
63class MguIO extends Bundle {
64  val in = new Bundle {
65    val src = Input(UInt(128.W))
66    val old_src = Input(UInt(128.W))
67    val mask = Input(UInt(128.W))
68    val isSegment = Input(Bool())
69    val info = Input(new VecInfo)
70  }
71  val out = new Bundle {
72    val vd = Output(UInt(128.W))
73  }
74}
75
76class VecInfo extends Bundle {
77  val vm = Bool()
78  val ta = Bool()
79  val ma = Bool()
80  val vl = UInt(8.W)
81  val vstart = UInt(7.W)
82  val eew = UInt(4.W)
83  val uopIdx = UInt(5.W)                //TODO: uopIdx width need to be paramterized, be consistent with Bundles.DecodeInst.uopIdx
84}
85
86object VerilogMgu extends App {
87  println("Generating the Mgu hardware")
88  emitVerilog(new Mgu(), Array("--target-dir", "build/vifu"))
89}