History log of /XiangShan/src/main/scala/xiangshan/backend/dispatch/ (Results 301 – 325 of 410)
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0e1f527308-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix dispatchPtr update when nested replay and cancel

554e49ab08-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: support nested replay and cancel

7230272008-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix inReplayWalk logic

fdd269b708-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix dispatchPtr update logic when dequeue

f506e33b08-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: rewrite index update logic, support preg state replay

7695ca7908-Aug-2020 Yinan Xu <[email protected]>

dispatch: support replay preg status

ab9aff1307-Aug-2020 Yinan Xu <[email protected]>

roq: fix memRedirect logic

de59342307-Aug-2020 William Wang <[email protected]>

Dispatch: fix commitType decode logic

a3edac5207-Aug-2020 Yinan Xu <[email protected]>

commitType: rename dpqType to commitType

3dd5b7c107-Aug-2020 Yinan Xu <[email protected]>

loadunit: fix l4_out flush

c105c2d306-Aug-2020 Yinan Xu <[email protected]>

lsroq: rename moq to lsroq


/XiangShan/debug/cputest.sh
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala
Dispatch.scala
Dispatch1.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache.scala
/XiangShan/src/main/scala/xiangshan/cache/dtlb.scala
/XiangShan/src/main/scala/xiangshan/cache/refill.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Btb.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala
/XiangShan/src/main/scala/xiangshan/mem/Memend.scala
/XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala
/XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala
/XiangShan/src/test/csrc/ram.cpp
/XiangShan/src/test/scala/top/XSSim.scala
/XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
27f5ce5e05-Aug-2020 Yinan Xu <[email protected]>

dispatch1: dont cancel when isReplay

0494b83305-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix replay count

a42f2d4604-Aug-2020 linjiawei <[email protected]>

Dispatch: use mem instead vector


/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/debug/Makefile
/XiangShan/scripts/statistics.py
/XiangShan/src/main/scala/device/AXI4UART.scala
/XiangShan/src/main/scala/noop/EXU.scala
/XiangShan/src/main/scala/noop/NOOPTrap.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Parameters.scala
/XiangShan/src/main/scala/top/TopMain.scala
/XiangShan/src/main/scala/utils/LogUtils.scala
/XiangShan/src/main/scala/utils/ParallelMux.scala
/XiangShan/src/main/scala/utils/PriorityMuxDefault.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala
DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Btb.scala
/XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala
/XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala
/XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala
/XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala
/XiangShan/src/test/csrc/common.h
/XiangShan/src/test/csrc/device.cpp
/XiangShan/src/test/csrc/difftest.cpp
/XiangShan/src/test/csrc/difftest.h
/XiangShan/src/test/csrc/emu.cpp
/XiangShan/src/test/csrc/emu.h
/XiangShan/src/test/csrc/main.cpp
/XiangShan/src/test/csrc/snapshot.cpp
/XiangShan/src/test/csrc/snapshot.h
/XiangShan/src/test/csrc/uart.cpp
/XiangShan/src/test/scala/top/SimMMIO.scala
/XiangShan/src/test/scala/top/XSSim.scala
/XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala
/XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala
/XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala
/XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala
/XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala
/XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
10ae8e4d04-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: add replay log

ca58ecbd04-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix ptr update logic

88a8316404-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix walk counter

40bb791c04-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix dequeue check

ab6830b904-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: walk if there're bubbles

a21e813803-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: fix cancel logic

23f0303903-Aug-2020 Yinan Xu <[email protected]>

dispatch1: fix canEnqueue using fpIndex and lsIndex

8bdbde1e02-Aug-2020 William Wang <[email protected]>

Mem: use moqIdx to mark commited store in lsroq

862a470002-Aug-2020 Yinan Xu <[email protected]>

dispatch queue: pop up invalid entries

b3d0909901-Aug-2020 Yinan Xu <[email protected]>

dispatch1: send dpqType to roq instead of dispatch queue

e5d116eb01-Aug-2020 Yinan Xu <[email protected]>

dispatch1: fix recv condition

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