xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision c105c2d33d0759193133e2489a231bad9d99a0a8) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.backend.ALUOpType
7import utils._
8import chisel3.util.experimental.BoringUtils
9import xiangshan.backend.decode.XSTrap
10
11trait BimParams extends HasXSParameter {
12  val BimBanks = PredictWidth
13  val BimSize = 4096
14  val nRows = BimSize / BimBanks
15}
16
17class BIM extends BasePredictor with BimParams{
18  class BIMResp extends Resp {
19    val ctrs = Vec(PredictWidth, UInt(2.W))
20  }
21  class BIMMeta extends Meta {
22    val ctrs = Vec(PredictWidth, UInt(2.W))
23  }
24  class BIMFromOthers extends FromOthers {}
25
26  class BIMIO extends DefaultBasePredictorIO {
27    val resp = Output(new BIMResp)
28    val meta = Output(new BIMMeta)
29  }
30
31  override val io = IO(new BIMIO)
32  // Update logic
33  // 1 calculate new 2-bit saturated counter value
34  def satUpdate(old: UInt, len: Int, taken: Bool): UInt = {
35    val oldSatTaken = old === ((1 << len)-1).U
36    val oldSatNotTaken = old === 0.U
37    Mux(oldSatTaken && taken, ((1 << len)-1).U,
38      Mux(oldSatNotTaken && !taken, 0.U,
39        Mux(taken, old + 1.U, old - 1.U)))
40  }
41
42  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
43
44  val pcLatch = RegEnable(io.pc.bits, io.pc.valid)
45
46  val bim = List.fill(BimBanks) {
47    Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true))
48  }
49
50  val doing_reset = RegInit(true.B)
51  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
52  resetRow := resetRow + doing_reset
53  when (resetRow === (nRows-1).U) { doing_reset := false.B }
54
55  val baseBank = bimAddr.getBank(io.pc.bits)
56
57  val realMask = circularShiftRight(io.inMask, BimBanks, baseBank)
58
59  // those banks whose indexes are less than baseBank are in the next row
60  val isInNextRow = VecInit((0 until BtbBanks).map(_.U < baseBank))
61
62  val baseRow = bimAddr.getBankIdx(io.pc.bits)
63
64  val realRow = VecInit((0 until BimBanks).map(b => Mux(isInNextRow(b.U), (baseRow+1.U)(log2Up(nRows)-1, 0), baseRow)))
65
66  val realRowLatch = VecInit(realRow.map(RegEnable(_, enable=io.pc.valid)))
67
68  for (b <- 0 until BimBanks) {
69    bim(b).reset                := reset.asBool
70    bim(b).io.r.req.valid       := realMask(b) && io.pc.valid
71    bim(b).io.r.req.bits.setIdx := realRow(b)
72  }
73
74  val bimRead = VecInit(bim.map(_.io.r.resp.data(0)))
75
76  val baseBankLatch = bimAddr.getBank(pcLatch)
77
78  // e.g: baseBank == 5 => (5, 6,..., 15, 0, 1, 2, 3, 4)
79  val bankIdxInOrder = VecInit((0 until BimBanks).map(b => (baseBankLatch +& b.U)(log2Up(BimBanks)-1, 0)))
80
81  for (b <- 0 until BimBanks) {
82    val ctr = bimRead(bankIdxInOrder(b))
83    io.resp.ctrs(b)  := ctr
84    io.meta.ctrs(b)  := ctr
85  }
86
87  val u = io.update.bits.ui
88
89  val updateBank = bimAddr.getBank(u.pc)
90  val updateRow = bimAddr.getBankIdx(u.pc)
91
92  val oldCtr = u.brInfo.bimCtr
93  val newTaken = u.taken
94  val oldSaturated = u.taken && oldCtr === 3.U || !u.taken && oldCtr === 0.U
95
96  val needToUpdate = io.update.valid && !oldSaturated && u.pd.isBr
97
98  for (b <- 0 until BimBanks) {
99    bim(b).io.w.req.valid := needToUpdate && b.U === updateBank || doing_reset
100    bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow)
101    bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), satUpdate(oldCtr, 2, newTaken))
102  }
103}