1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig} 7import top.Parameters 8import xiangshan.backend._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.backend.exu.ExuParameters 11import xiangshan.frontend._ 12import xiangshan.mem._ 13import utils._ 14import xiangshan.mem.cache.DcacheUserBundle 15 16case class XSCoreParameters 17( 18 XLEN: Int = 64, 19 HasMExtension: Boolean = true, 20 HasCExtension: Boolean = true, 21 HasDiv: Boolean = true, 22 HasICache: Boolean = true, 23 HasDCache: Boolean = true, 24 EnableStoreQueue: Boolean = true, 25 AddrBits: Int = 64, 26 VAddrBits: Int = 39, 27 PAddrBits: Int = 32, 28 HasFPU: Boolean = true, 29 FectchWidth: Int = 8, 30 EnableBPU: Boolean = true, 31 EnableBPD: Boolean = false, 32 EnableRAS: Boolean = false, 33 EnableLB: Boolean = false, 34 HistoryLength: Int = 64, 35 BtbSize: Int = 256, 36 JbtacSize: Int = 1024, 37 JbtacBanks: Int = 8, 38 RasSize: Int = 16, 39 CacheLineSize: Int = 512, 40 UBtbWays: Int = 16, 41 BtbWays: Int = 2, 42 IBufSize: Int = 64, 43 DecodeWidth: Int = 6, 44 RenameWidth: Int = 6, 45 CommitWidth: Int = 6, 46 BrqSize: Int = 16, 47 IssQueSize: Int = 8, 48 NRPhyRegs: Int = 128, 49 NRIntReadPorts: Int = 8, 50 NRIntWritePorts: Int = 8, 51 NRFpReadPorts: Int = 14, 52 NRFpWritePorts: Int = 8, 53 MoqSize: Int = 16, 54 RoqSize: Int = 32, 55 IntDqDeqWidth: Int = 4, 56 FpDqDeqWidth: Int = 4, 57 LsDqDeqWidth: Int = 4, 58 dpParams: DispatchParameters = DispatchParameters( 59 DqEnqWidth = 4, 60 IntDqSize = 64, 61 FpDqSize = 64, 62 LsDqSize = 64, 63 IntDqDeqWidth = 4, 64 FpDqDeqWidth = 4, 65 LsDqDeqWidth = 4 66 ), 67 exuParameters: ExuParameters = ExuParameters( 68 JmpCnt = 1, 69 AluCnt = 4, 70 MulCnt = 0, 71 MduCnt = 2, 72 FmacCnt = 0, 73 FmiscCnt = 0, 74 FmiscDivSqrtCnt = 0, 75 LduCnt = 2, 76 StuCnt = 2 77 ), 78 LoadPipelineWidth: Int = 2, 79 StorePipelineWidth: Int = 2, 80 StoreBufferSize: Int = 16, 81 RefillSize: Int = 512 82) 83 84 85trait HasXSParameter { 86 87 val core = Parameters.get.coreParameters 88 val env = Parameters.get.envParameters 89 90 val XLEN = core.XLEN 91 val HasMExtension = core.HasMExtension 92 val HasCExtension = core.HasCExtension 93 val HasDiv = core.HasDiv 94 val HasIcache = core.HasICache 95 val HasDcache = core.HasDCache 96 val EnableStoreQueue = core.EnableStoreQueue 97 val AddrBits = core.AddrBits // AddrBits is used in some cases 98 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 99 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 100 val AddrBytes = AddrBits / 8 // unused 101 val DataBits = XLEN 102 val DataBytes = DataBits / 8 103 val HasFPU = core.HasFPU 104 val FetchWidth = core.FectchWidth 105 val PredictWidth = FetchWidth * 2 106 val EnableBPU = core.EnableBPU 107 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 108 val EnableRAS = core.EnableRAS 109 val EnableLB = core.EnableLB 110 val HistoryLength = core.HistoryLength 111 val BtbSize = core.BtbSize 112 // val BtbWays = 4 113 val BtbBanks = PredictWidth 114 // val BtbSets = BtbSize / BtbWays 115 val JbtacSize = core.JbtacSize 116 val JbtacBanks = core.JbtacBanks 117 val RasSize = core.RasSize 118 val CacheLineSize = core.CacheLineSize 119 val CacheLineHalfWord = CacheLineSize / 16 120 val ExtHistoryLength = HistoryLength * 2 121 val UBtbWays = core.UBtbWays 122 val BtbWays = core.BtbWays 123 val IBufSize = core.IBufSize 124 val DecodeWidth = core.DecodeWidth 125 val RenameWidth = core.RenameWidth 126 val CommitWidth = core.CommitWidth 127 val BrqSize = core.BrqSize 128 val IssQueSize = core.IssQueSize 129 val BrTagWidth = log2Up(BrqSize) 130 val NRPhyRegs = core.NRPhyRegs 131 val PhyRegIdxWidth = log2Up(NRPhyRegs) 132 val MoqSize = core.MoqSize // 64 133 val RoqSize = core.RoqSize 134 val InnerRoqIdxWidth = log2Up(RoqSize) 135 val RoqIdxWidth = InnerRoqIdxWidth + 1 136 val InnerMoqIdxWidth = log2Up(MoqSize) 137 val MoqIdxWidth = InnerMoqIdxWidth + 1 138 val IntDqDeqWidth = core.IntDqDeqWidth 139 val FpDqDeqWidth = core.FpDqDeqWidth 140 val LsDqDeqWidth = core.LsDqDeqWidth 141 val dpParams = core.dpParams 142 val exuParameters = core.exuParameters 143 val NRIntReadPorts = core.NRIntReadPorts 144 val NRIntWritePorts = core.NRIntWritePorts 145 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 146 val NRFpReadPorts = core.NRFpReadPorts 147 val NRFpWritePorts = core.NRFpWritePorts 148 val LoadPipelineWidth = core.LoadPipelineWidth 149 val StorePipelineWidth = core.StorePipelineWidth 150 val StoreBufferSize = core.StoreBufferSize 151 val RefillSize = core.RefillSize 152} 153 154trait HasXSLog { this: Module => 155 implicit val moduleName: String = this.name 156} 157 158abstract class XSModule extends Module 159 with HasXSParameter 160 with HasExceptionNO 161 with HasXSLog 162 163//remove this trait after impl module logic 164trait NeedImpl { this: Module => 165 override protected def IO[T <: Data](iodef: T): T = { 166 val io = chisel3.experimental.IO(iodef) 167 io <> DontCare 168 io 169 } 170} 171 172abstract class XSBundle extends Bundle 173 with HasXSParameter 174 175case class EnviromentParameters 176( 177 FPGAPlatform: Boolean = true, 178 EnableDebug: Boolean = false 179) 180 181object AddressSpace extends HasXSParameter { 182 // (start, size) 183 // address out of MMIO will be considered as DRAM 184 def mmio = List( 185 (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC 186 (0x40000000L, 0x40000000L) // external devices 187 ) 188 189 def isMMIO(addr: UInt): Bool = mmio.map(range => { 190 require(isPow2(range._2)) 191 val bits = log2Up(range._2) 192 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 193 }).reduce(_ || _) 194} 195 196 197class XSCore extends XSModule { 198 val io = IO(new Bundle { 199 val imem = new SimpleBusC 200 val dmem = new SimpleBusC 201 val mmio = new SimpleBusUC 202 val frontend = Flipped(new SimpleBusUC()) 203 }) 204 205 io.imem <> DontCare 206 207 val DcacheUserBundleWidth = (new DcacheUserBundle).getWidth 208 209 val dmemXbar = Module(new SimpleBusCrossbarNto1(n = 2, userBits = DcacheUserBundleWidth)) 210 211 val front = Module(new Frontend) 212 val backend = Module(new Backend) 213 val mem = Module(new Memend) 214 215 front.io.backend <> backend.io.frontend 216 mem.io.backend <> backend.io.mem 217 218 backend.io.memMMU.imem <> DontCare 219 220 val dtlb = TLB( 221 in = mem.io.dmem, 222 mem = dmemXbar.io.in(1), 223 flush = false.B, 224 csrMMU = backend.io.memMMU.dmem 225 )(TLBConfig(name = "dtlb", totalEntry = 64, userBits = DcacheUserBundleWidth)) 226 dmemXbar.io.in(0) <> dtlb.io.out 227 // dmemXbar.io.in(1) <> io.frontend 228 229 io.frontend <> DontCare 230 231 io.dmem <> Cache( 232 in = dmemXbar.io.out, 233 mmio = Seq(io.mmio), 234 flush = "b00".U, 235 empty = dtlb.io.cacheEmpty, 236 enable = HasDcache 237 )(CacheConfig(name = "dcache", userBits = DcacheUserBundleWidth)) 238 239} 240