xref: /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala (revision c105c2d33d0759193133e2489a231bad9d99a0a8)
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import device.RAMHelper
6import xiangshan._
7import utils._
8
9trait HasIFUConst { this: XSModule =>
10  val resetVector = 0x80000000L//TODO: set reset vec
11  val groupAlign = log2Up(FetchWidth * 4 * 2)
12  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
13  // each 1 bit in mask stands for 2 Bytes
14  def mask(pc: UInt): UInt = (Fill(PredictWidth * 2, 1.U(1.W)) >> pc(groupAlign - 1, 1))(PredictWidth - 1, 0)
15  def snpc(pc: UInt): UInt = pc + (PopCount(mask(pc)) << 1)
16}
17
18class IFUIO extends XSBundle
19{
20  val fetchPacket = DecoupledIO(new FetchPacket)
21  val redirect = Flipped(ValidIO(new Redirect))
22  val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
23  val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
24  val icacheReq = DecoupledIO(new FakeIcacheReq)
25  val icacheResp = Flipped(DecoupledIO(new FakeIcacheResp))
26  val icacheFlush = Output(UInt(2.W))
27}
28
29
30class IFU extends XSModule with HasIFUConst
31{
32  val io = IO(new IFUIO)
33  val bpu = if (EnableBPU) Module(new BPU) else Module(new FakeBPU)
34  val pd = Module(new PreDecode)
35
36  val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B)
37  val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B)
38
39  if4_flush := io.redirect.valid
40  if3_flush := if4_flush || if4_redirect
41  if2_flush := if3_flush || if3_redirect
42  if1_flush := if2_flush || if2_redirect
43
44  //********************** IF1 ****************************//
45  val if1_valid = !reset.asBool
46  val if1_npc = WireInit(0.U(VAddrBits.W))
47  val if2_ready = WireInit(false.B)
48  val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready
49
50  // val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W))))
51  val extHist = RegInit(VecInit(Seq.fill(ExtHistoryLength)(0.U(1.W))))
52  val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W))
53  val shiftPtr = WireInit(false.B)
54  val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W))
55  val ptr = Mux(shiftPtr, newPtr, headPtr)
56  when (shiftPtr) { headPtr := newPtr }
57  val hist = Wire(Vec(HistoryLength, UInt(1.W)))
58  for (i <- 0 until HistoryLength) {
59    hist(i) := extHist(ptr + i.U)
60  }
61
62  newPtr := headPtr
63  shiftPtr := false.B
64
65  //********************** IF2 ****************************//
66  val if2_valid = RegEnable(next = if1_valid, init = false.B, enable = if1_fire)
67  val if3_ready = WireInit(false.B)
68  val if2_fire = if2_valid && if3_ready && !if2_flush
69  val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire)
70  val if2_snpc = snpc(if2_pc)
71  val if2_histPtr = RegEnable(ptr, if1_fire)
72  if2_ready := if2_fire || !if2_valid || if2_flush
73  when (if2_flush) { if2_valid := if1_fire }
74  .elsewhen (if1_fire) { if2_valid := if1_valid }
75  .elsewhen (if2_fire) { if2_valid := false.B }
76
77  when (RegNext(reset.asBool) && !reset.asBool) {
78    if1_npc := resetVector.U(VAddrBits.W)
79  }.elsewhen (if2_fire) {
80    if1_npc := if2_snpc
81  }.otherwise {
82    if1_npc := RegNext(if1_npc)
83  }
84
85  val if2_bp = bpu.io.out(0).bits
86  if2_redirect := if2_fire && bpu.io.out(0).valid && if2_bp.redirect// && !if2_bp.saveHalfRVI
87  when (if2_redirect) {
88    if1_npc := if2_bp.target
89  }
90
91  when (if2_fire && (if2_bp.taken || if2_bp.hasNotTakenBrs)) {
92    shiftPtr := true.B
93    newPtr := headPtr - 1.U
94    hist(0) := if2_bp.taken.asUInt
95    extHist(newPtr) := if2_bp.taken.asUInt
96  }
97
98  //********************** IF3 ****************************//
99  val if3_valid = RegEnable(next = if2_valid, init = false.B, enable = if2_fire)
100  val if4_ready = WireInit(false.B)
101  val if3_fire = if3_valid && if4_ready && io.icacheResp.valid && !if3_flush
102  val if3_pc = RegEnable(if2_pc, if2_fire)
103  val if3_histPtr = RegEnable(if2_histPtr, if2_fire)
104  if3_ready := if3_fire || !if3_valid || if3_flush
105  when (if3_flush) { if3_valid := false.B }
106  .elsewhen (if2_fire) { if3_valid := if2_valid }
107  .elsewhen (if3_fire) { if3_valid := false.B }
108
109  val if3_bp = bpu.io.out(1).bits
110
111  class PrevHalfInstr extends Bundle {
112    val valid = Bool()
113    val taken = Bool()
114    val fetchpc = UInt(VAddrBits.W) // only for debug
115    val idx = UInt(VAddrBits.W) // only for debug
116    val pc = UInt(VAddrBits.W)
117    val target = UInt(VAddrBits.W)
118    val instr = UInt(16.W)
119  }
120
121  val if3_prevHalfInstr = RegInit(0.U.asTypeOf(new PrevHalfInstr))
122  val if4_prevHalfInstr = Wire(new PrevHalfInstr)
123  when (if4_prevHalfInstr.valid) {
124    if3_prevHalfInstr := if4_prevHalfInstr
125  }
126  val prevHalfInstr = Mux(if4_prevHalfInstr.valid, if4_prevHalfInstr, if3_prevHalfInstr)
127
128  val if3_hasPrevHalfInstr = prevHalfInstr.valid && (prevHalfInstr.pc + 2.U) === if3_pc
129  if3_redirect := if3_fire && bpu.io.out(1).valid && (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.redirect/* && !if3_bp.saveHalfRVI*/ )
130  when (if3_redirect) {
131    if1_npc := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken, prevHalfInstr.target, if3_bp.target)
132  }
133
134  when (if3_fire && if3_redirect) {
135    shiftPtr := true.B
136    newPtr := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr)
137    hist(0) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs,
138      (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt,
139      extHist(if3_histPtr))
140    extHist(newPtr) := Mux(if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken || if3_bp.hasNotTakenBrs,
141      (if3_hasPrevHalfInstr && prevHalfInstr.taken || if3_bp.taken).asUInt,
142      extHist(if3_histPtr))
143  }
144
145
146
147  // val prev_half_valid = RegInit(false.B)
148  // val prev_half_redirect = RegInit(false.B)
149  // val prev_half_fetchpc = Reg(UInt(VAddrBits.W))
150  // val prev_half_idx = Reg(UInt(log2Up(PredictWidth).W))
151  // val prev_half_tgt = Reg(UInt(VAddrBits.W))
152  // val prev_half_taken = RegInit(false.B)
153  // val prev_half_instr = Reg(UInt(16.W))
154  // when (if3_flush) {
155  //   prev_half_valid := false.B
156  //   prev_half_redirect := false.B
157  // }.elsewhen (if3_fire && if3_bp.saveHalfRVI) {
158  //   prev_half_valid := true.B
159  //   prev_half_redirect := if3_bp.redirect && bpu.io.out(1).valid
160  //   prev_half_fetchpc := if3_pc
161  //   val idx = Mux(if3_bp.redirect && bpu.io.out(1).valid, if3_bp.jmpIdx, PopCount(mask(if3_pc)) - 1.U)
162  //   prev_half_idx := idx
163  //   prev_half_tgt := if3_bp.target
164  //   prev_half_taken := if3_bp.taken
165  //   prev_half_instr := pd.io.out.instrs(idx)(15, 0)
166  // }.elsewhen (if3_fire) {
167  //   prev_half_valid := false.B
168  //   prev_half_redirect := false.B
169  // }
170
171  // when (bpu.io.out(1).valid && if3_fire) {
172  //   when (prev_half_valid && prev_half_taken) {
173  //     if3_redirect := true.B
174  //     if1_npc := prev_half_tgt
175  //     shiftPtr := true.B
176  //     newPtr := if3_histPtr - 1.U
177  //     hist(0) := 1.U
178  //     extHist(newPtr) := 1.U
179  //   }.elsewhen (if3_bp.redirect && !if3_bp.saveHalfRVI) {
180  //     if3_redirect := true.B
181  //     if1_npc := if3_bp.target
182  //     shiftPtr := true.B
183  //     newPtr := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr)
184  //     hist(0) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr))
185  //     extHist(newPtr) := Mux(if3_bp.taken || if3_bp.hasNotTakenBrs, if3_bp.taken.asUInt, extHist(if3_histPtr))
186  //   }.elsewhen (if3_bp.saveHalfRVI) {
187  //     if3_redirect := true.B
188  //     if1_npc := snpc(if3_pc)
189  //     shiftPtr := true.B
190  //     newPtr := Mux(if3_bp.hasNotTakenBrs, if3_histPtr - 1.U, if3_histPtr)
191  //     hist(0) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr))
192  //     extHist(newPtr) := Mux(if3_bp.hasNotTakenBrs, 0.U, extHist(if3_histPtr))
193  //   }.otherwise {
194  //     if3_redirect := false.B
195  //   }
196  // }.otherwise {
197  //   if3_redirect := false.B
198  // }
199
200
201  //********************** IF4 ****************************//
202  val if4_pd = RegEnable(pd.io.out, if3_fire)
203  val if4_valid = RegInit(false.B)
204  val if4_fire = if4_valid && io.fetchPacket.ready
205  val if4_pc = RegEnable(if3_pc, if3_fire)
206  val if4_histPtr = RegEnable(if3_histPtr, if3_fire)
207  if4_ready := (if4_fire || !if4_valid || if4_flush) && GTimer() > 500.U
208  when (if4_flush)     { if4_valid := false.B }
209  .elsewhen (if3_fire) { if4_valid := if3_valid }
210  .elsewhen(if4_fire)  { if4_valid := false.B }
211
212  val if4_bp = Wire(new BranchPrediction)
213  if4_bp := bpu.io.out(2).bits
214  // TODO: c_jal
215  val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx)
216  val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN)
217  if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target)
218  if4_bp.redirect := bpu.io.out(2).bits.redirect || if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken && if4_cfi_jal_tgt =/= bpu.io.out(2).bits.target
219
220  if4_prevHalfInstr := 0.U.asTypeOf(new PrevHalfInstr)
221  when (bpu.io.out(2).valid && if4_fire && if4_bp.saveHalfRVI) {
222    if4_prevHalfInstr.valid := true.B
223    if4_prevHalfInstr.taken := if4_bp.taken
224    if4_prevHalfInstr.fetchpc := if4_pc
225    if4_prevHalfInstr.idx := PopCount(mask(if4_pc)) - 1.U
226    if4_prevHalfInstr.pc := if4_pd.pc(if4_prevHalfInstr.idx)
227    if4_prevHalfInstr.target := if4_bp.target
228    if4_prevHalfInstr.instr := if4_pd.instrs(if4_prevHalfInstr.idx)(15, 0)
229  }
230
231  when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) {
232    if4_redirect := true.B
233    shiftPtr := true.B
234    newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr)
235    hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr))
236    extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr))
237    when (if4_bp.saveHalfRVI) {
238      if1_npc := snpc(if4_pc)
239    }.otherwise {
240      if1_npc := if4_bp.target
241    }
242  }.elsewhen (bpu.io.out(2).valid && if4_fire/* && !if4_bp.redirect*/) {
243    when (if4_bp.saveHalfRVI && if4_bp.taken) {
244      if4_redirect := true.B
245      if1_npc := snpc(if4_pc)
246      shiftPtr := true.B
247      newPtr := if4_histPtr - 1.U
248      hist(0) := 1.U
249      extHist(newPtr) := 1.U
250    }.otherwise {
251      if4_redirect := false.B
252    }
253  }.otherwise {
254    if4_redirect := false.B
255  }
256
257
258
259  // when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) {
260  //   when (!if4_bp.saveHalfRVI) {
261  //     if4_redirect := true.B
262  //     // if1_npc := if4_bp.target
263  //     if1_npc := Mux(if4_bp.taken, if4_bp.target, snpc(if4_pc))
264
265  //     shiftPtr := true.B
266  //     newPtr := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr)
267  //     hist(0) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr))
268  //     extHist(newPtr) := Mux(if4_bp.taken || if4_bp.hasNotTakenBrs, if4_bp.taken.asUInt, extHist(if4_histPtr))
269
270  //   }.otherwise {
271  //     if4_redirect := true.B
272  //     if1_npc := snpc(if4_pc)
273
274  //     prev_half_valid := true.B
275  //     prev_half_redirect := true.B
276  //     prev_half_fetchpc := if4_pc
277  //     val idx = PopCount(mask(if4_pc)) - 1.U
278  //     prev_half_idx := idx
279  //     prev_half_tgt := if4_bp.target
280  //     prev_half_taken := if4_bp.taken
281  //     prev_half_instr := if4_pd.instrs(idx)(15, 0)
282
283  //     shiftPtr := true.B
284  //     newPtr := Mux(if4_bp.hasNotTakenBrs, if4_histPtr - 1.U, if4_histPtr)
285  //     hist(0) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr))
286  //     extHist(newPtr) := Mux(if4_bp.hasNotTakenBrs, 0.U, extHist(if4_histPtr))
287  //   }
288  // }.otherwise {
289  //   if4_redirect := false.B
290  // }
291
292  when (io.outOfOrderBrInfo.valid) {
293    shiftPtr := true.B
294    newPtr := io.outOfOrderBrInfo.bits.brInfo.histPtr - 1.U
295    hist(0) := io.outOfOrderBrInfo.bits.taken
296    extHist(newPtr) := io.outOfOrderBrInfo.bits.taken
297  }
298
299  when (io.redirect.valid) {
300    if1_npc := io.redirect.bits.target
301  }
302
303  io.icacheReq.valid := if1_valid && if2_ready
304  io.icacheReq.bits.addr := if1_npc
305  io.icacheResp.ready := if3_ready
306  io.icacheFlush := Cat(if3_flush, if2_flush)
307
308  val inOrderBrHist = Wire(Vec(HistoryLength, UInt(1.W)))
309  (0 until HistoryLength).foreach(i => inOrderBrHist(i) := extHist(i.U + io.inOrderBrInfo.bits.brInfo.histPtr))
310  bpu.io.inOrderBrInfo.valid := io.inOrderBrInfo.valid
311  bpu.io.inOrderBrInfo.bits := BranchUpdateInfoWithHist(io.inOrderBrInfo.bits, inOrderBrHist.asUInt)
312  // bpu.io.flush := Cat(if4_flush, if3_flush, if2_flush)
313  bpu.io.flush := VecInit(if2_flush, if3_flush, if4_flush)
314  bpu.io.in.valid := if1_fire
315  bpu.io.in.bits.pc := if1_npc
316  bpu.io.in.bits.hist := hist.asUInt
317  bpu.io.in.bits.inMask := mask(if1_npc)
318  bpu.io.out(0).ready := if2_fire
319  bpu.io.out(1).ready := if3_fire
320  bpu.io.out(2).ready := if4_fire
321  bpu.io.predecode.valid := if4_valid
322  bpu.io.predecode.bits.mask := if4_pd.mask
323  bpu.io.predecode.bits.pd := if4_pd.pd
324  bpu.io.branchInfo.ready := if4_fire
325
326  pd.io.in := io.icacheResp.bits
327  pd.io.prev.valid := if3_hasPrevHalfInstr
328  pd.io.prev.bits := prevHalfInstr.target
329
330  io.fetchPacket.valid := if4_valid && !io.redirect.valid
331  io.fetchPacket.bits.instrs := if4_pd.instrs
332  io.fetchPacket.bits.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx)))
333  io.fetchPacket.bits.pc := if4_pd.pc
334  (0 until PredictWidth).foreach(i => io.fetchPacket.bits.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U))
335  when (if4_bp.taken) {
336    io.fetchPacket.bits.pnpc(if4_bp.jmpIdx) := if4_bp.target
337  }
338  io.fetchPacket.bits.brInfo := bpu.io.branchInfo.bits
339  (0 until PredictWidth).foreach(i => io.fetchPacket.bits.brInfo(i).histPtr := if4_histPtr)
340  io.fetchPacket.bits.pd := if4_pd.pd
341
342  // debug info
343  XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n")
344  XSDebug(io.icacheFlush(0).asBool, "Flush icache stage2...\n")
345  XSDebug(io.icacheFlush(1).asBool, "Flush icache stage3...\n")
346  XSDebug(io.redirect.valid, "Redirect from backend! isExcp=%d isMisPred=%d isReplay=%d pc=%x\n",
347    io.redirect.bits.isException, io.redirect.bits.isMisPred, io.redirect.bits.isReplay, io.redirect.bits.pc)
348  XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.target)} brTag=${io.redirect.bits.brTag}\n")
349
350  XSDebug("[IF1] v=%d     fire=%d            flush=%d pc=%x ptr=%d mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, ptr, mask(if1_npc))
351  XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_histPtr, if2_snpc)
352  XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr)
353  XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr)
354
355  XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr)
356  XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr)
357  XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt)
358  XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt)
359
360  XSDebug("[IF2][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.redirect, if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI)
361
362  XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", io.icacheResp.valid, io.icacheResp.ready, io.icacheResp.bits.pc, io.icacheResp.bits.mask)
363  XSDebug("[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.redirect, if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI)
364  // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n",
365  //   prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr)
366  XSDebug("[IF3][    prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n",
367    prevHalfInstr.valid, prevHalfInstr.taken, prevHalfInstr.fetchpc, prevHalfInstr.idx, prevHalfInstr.pc, prevHalfInstr.target, prevHalfInstr.instr)
368  XSDebug("[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n\n",
369    if3_prevHalfInstr.valid, if3_prevHalfInstr.taken, if3_prevHalfInstr.fetchpc, if3_prevHalfInstr.idx, if3_prevHalfInstr.pc, if3_prevHalfInstr.target, if3_prevHalfInstr.instr)
370
371
372  XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask)
373  XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI)
374  XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal!  instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt)
375  XSDebug("[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n",
376    if4_prevHalfInstr.valid, if4_prevHalfInstr.taken, if4_prevHalfInstr.fetchpc, if4_prevHalfInstr.idx, if4_prevHalfInstr.pc, if4_prevHalfInstr.target, if4_prevHalfInstr.instr)
377  XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask)
378  for (i <- 0 until PredictWidth) {
379    XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n",
380      io.fetchPacket.bits.mask(i),
381      io.fetchPacket.bits.instrs(i),
382      io.fetchPacket.bits.pc(i),
383      io.fetchPacket.bits.pnpc(i),
384      io.fetchPacket.bits.pd(i).isRVC,
385      io.fetchPacket.bits.pd(i).brType,
386      io.fetchPacket.bits.pd(i).isCall,
387      io.fetchPacket.bits.pd(i).isRet
388    )
389  }
390}