MemBlock: use only one port for both vector loads and stores

backend: avoid to use VfRD port 0

Backend: WBDataPath and ROB support vlsu(vld res merge and exceptionGen)

Parameters: modify read port index

Add VLSU

* miscs: optimize code style

* vector: add VLSU param system and redefine vector lq io

* VLUopQueue: add flow split and address generation logic

* VLUopQueue: add flow issue and writebac

Add VLSU

* miscs: optimize code style

* vector: add VLSU param system and redefine vector lq io

* VLUopQueue: add flow split and address generation logic

* VLUopQueue: add flow issue and writeback logic

* VLUopQueue: set vstart for elements with exception

* VLUopQueue: handle unit-stride fof loads

* VLUopQueue: implement vector masking according to vm

* vector: rewrite vector store io

* VlFlowQueue: add enqueue and dequeue logic

* VLFlowQueue: fix some coding problem

* VlFlowQueue: add issue, replay and result logic

* VLFlowQueue: add redirect logic

* Rob: fix compilation error

* vector: remove stale codes

* vector: add VSUopQueue and fix bugs for vector load

* backbone: add vector load/store execution paths

* VSFlowQueue: Basic function

* VLUopQueue: add redirect logic for load-load violation

* VSFlowQueue: fix some compile problems

* VSUopQueue: add signal to indicate whether a flow is the last one

* VSFlowQueue: inform scala sq when vector store finished

* StoreQueue: maintain sequential retirement between scalar & vector stores

* LoadQueueRAW: handle violation between vector stores & scalar loads

* LDU: add vector store to scalar load forwarding

* XSCore: fix writeback width of MemBlock

* vector: fix load/store whole register and masked unit-stride load/store emul, evl, flownum (#2383)

* VSFlowQueue: Support STLF

* VLFlowQueue: fix compile bug

* VSFlowQueue: fix compile problem

---------

Co-authored-by: xuzefan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: weidingliu <[email protected]>

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hpm: fix selection logic and typo (#1618) (#2483)

Co-authored-by: Chen Xi <[email protected]>

backend: fix compile errors

backend: refactor Dispatch2IqMemImp

backend: support hybrid unit

* filter not fake unit when generate bundles
* add fake exu unit
* hybrid unit use one load writeback port and one store writeback port

backend,mem: split hybrid units writeback bundle

memblock: make lsq enq width equals to LsDqDeqWidth

backend: support HybridUnit at Dispatch Stage

add hybrid unit

backend,mem: support HybridUnit

param,backend: modify regfile's r/w configs

3ld2st-for-new-backend

tmp: ideal int read ports

refactor: use banked IBuffer (#2441)

* ibuffer: refactor to raw Vec

- use banked register to reduce read port logic

ibuffer: fix assertion error

ibuffer: fix various typo assertion bug

i

refactor: use banked IBuffer (#2441)

* ibuffer: refactor to raw Vec

- use banked register to reduce read port logic

ibuffer: fix assertion error

ibuffer: fix various typo assertion bug

ibuffer: fix entry write mux

ibuffer: fix deqPtr movement

ibuffer: fix NBank larger than DecodeWidth

ibuffer: add comments about new design

config: change MinimalConfig IBufNBank back to 2

config: use DecodeWidth as IBufNBank

config: remove IBufNBank from XSCoreParameters

Revert "config: remove IBufNBank from XSCoreParameters"

This reverts commit 4da836590cc3af168e1cf2582269fc15394b514e.

Revert "config: use DecodeWidth as IBufNBank"

This reverts commit d04bddb551f846ad65db2a2cc903d26251be0ee8.

* ibuffer: use Mux1H to rewrite read port

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rv64v: replace i2f by i2v for vector instructions

rv64v: fix read port conflict

ftq: remove jmp/ldReplay/exception(redirectAhead) (#2420)

TODO: backend remove jmp/ldReplay/exception

RAS: fix counter size (#2399)

* RAS: fix counter size

* RAS: reduce counter width

DispatchQueue,param: increase LsDqDeqWidth by 2

param,backend: increace number of int pregs to 224

param,backend: modify regfile's r/w configs