xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 20a5248fc72cbfda1fdcbdfca05462d1f45b7939) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import huancun._
23import system.SoCParamsKey
24import xiangshan.backend.datapath.RdConfig._
25import xiangshan.backend.datapath.WbConfig._
26import xiangshan.backend.dispatch.DispatchParameters
27import xiangshan.backend.exu.ExeUnitParams
28import xiangshan.backend.fu.FuConfig._
29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler}
30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams}
31import xiangshan.backend.BackendParams
32import xiangshan.cache.DCacheParameters
33import xiangshan.cache.prefetch._
34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB}
35import xiangshan.frontend.icache.ICacheParameters
36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
37import xiangshan.frontend._
38import xiangshan.frontend.icache.ICacheParameters
39
40import freechips.rocketchip.diplomacy.AddressSet
41import system.SoCParamsKey
42import huancun._
43import huancun.debug._
44import xiangshan.cache.wpu.WPUParameters
45import coupledL2._
46import xiangshan.backend.datapath.WakeUpConfig
47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams}
48
49import scala.math.min
50
51case object XSTileKey extends Field[Seq[XSCoreParameters]]
52
53case object XSCoreParamsKey extends Field[XSCoreParameters]
54
55case class XSCoreParameters
56(
57  HasPrefetch: Boolean = false,
58  HartId: Int = 0,
59  XLEN: Int = 64,
60  VLEN: Int = 128,
61  ELEN: Int = 64,
62  HasMExtension: Boolean = true,
63  HasCExtension: Boolean = true,
64  HasDiv: Boolean = true,
65  HasICache: Boolean = true,
66  HasDCache: Boolean = true,
67  AddrBits: Int = 64,
68  VAddrBits: Int = 39,
69  HasFPU: Boolean = true,
70  HasVPU: Boolean = true,
71  HasCustomCSRCacheOp: Boolean = true,
72  FetchWidth: Int = 8,
73  AsidLength: Int = 16,
74  EnableBPU: Boolean = true,
75  EnableBPD: Boolean = true,
76  EnableRAS: Boolean = true,
77  EnableLB: Boolean = false,
78  EnableLoop: Boolean = true,
79  EnableSC: Boolean = true,
80  EnbaleTlbDebug: Boolean = false,
81  EnableJal: Boolean = false,
82  EnableFauFTB: Boolean = true,
83  UbtbGHRLength: Int = 4,
84  // HistoryLength: Int = 512,
85  EnableGHistDiff: Boolean = true,
86  EnableCommitGHistDiff: Boolean = true,
87  UbtbSize: Int = 256,
88  FtbSize: Int = 2048,
89  RasSize: Int = 32,
90  RasSpecSize: Int = 64,
91  RasCtrSize: Int = 8,
92  CacheLineSize: Int = 512,
93  FtbWays: Int = 4,
94  TageTableInfos: Seq[Tuple3[Int,Int,Int]] =
95  //       Sets  Hist   Tag
96    // Seq(( 2048,    2,    8),
97    //     ( 2048,    9,    8),
98    //     ( 2048,   13,    8),
99    //     ( 2048,   20,    8),
100    //     ( 2048,   26,    8),
101    //     ( 2048,   44,    8),
102    //     ( 2048,   73,    8),
103    //     ( 2048,  256,    8)),
104    Seq(( 4096,    8,    8),
105        ( 4096,   13,    8),
106        ( 4096,   32,    8),
107        ( 4096,  119,    8)),
108  ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] =
109  //      Sets  Hist   Tag
110    Seq(( 256,    4,    9),
111        ( 256,    8,    9),
112        ( 512,   13,    9),
113        ( 512,   16,    9),
114        ( 512,   32,    9)),
115  SCNRows: Int = 512,
116  SCNTables: Int = 4,
117  SCCtrBits: Int = 6,
118  SCHistLens: Seq[Int] = Seq(0, 4, 10, 16),
119  numBr: Int = 2,
120  branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
121    ((resp_in: BranchPredictionResp, p: Parameters) => {
122      val ftb = Module(new FTB()(p))
123      val ubtb =Module(new FauFTB()(p))
124      // val bim = Module(new BIM()(p))
125      val tage = Module(new Tage_SC()(p))
126      val ras = Module(new RAS()(p))
127      val ittage = Module(new ITTage()(p))
128      val preds = Seq(ubtb, tage, ftb, ittage, ras)
129      preds.map(_.io := DontCare)
130
131      // ubtb.io.resp_in(0)  := resp_in
132      // bim.io.resp_in(0)   := ubtb.io.resp
133      // btb.io.resp_in(0)   := bim.io.resp
134      // tage.io.resp_in(0)  := btb.io.resp
135      // loop.io.resp_in(0)  := tage.io.resp
136      ubtb.io.in.bits.resp_in(0) := resp_in
137      tage.io.in.bits.resp_in(0) := ubtb.io.out
138      ftb.io.in.bits.resp_in(0)  := tage.io.out
139      ittage.io.in.bits.resp_in(0)  := ftb.io.out
140      ras.io.in.bits.resp_in(0) := ittage.io.out
141
142      (preds, ras.io.out)
143    }),
144  IBufSize: Int = 48,
145  DecodeWidth: Int = 6,
146  RenameWidth: Int = 6,
147  CommitWidth: Int = 6,
148  MaxUopSize: Int = 65,
149  EnableRenameSnapshot: Boolean = true,
150  RenameSnapshotNum: Int = 4,
151  FtqSize: Int = 64,
152  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
153  IntLogicRegs: Int = 32,
154  FpLogicRegs: Int = 33,
155  VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig
156  VCONFIG_IDX: Int = 32,
157  NRPhyRegs: Int = 192,
158  VirtualLoadQueueSize: Int = 80,
159  LoadQueueRARSize: Int = 80,
160  LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2.
161  RollbackGroupSize: Int = 8,
162  LoadQueueReplaySize: Int = 72,
163  LoadUncacheBufferSize: Int = 20,
164  LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks
165  StoreQueueSize: Int = 64,
166  StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
167  StoreQueueForwardWithMask: Boolean = true,
168  VlsQueueSize: Int = 8,
169  RobSize: Int = 256,
170  RabSize: Int = 256,
171  IssueQueueSize: Int = 32,
172  dpParams: DispatchParameters = DispatchParameters(
173    IntDqSize = 16,
174    FpDqSize = 16,
175    LsDqSize = 18,
176    IntDqDeqWidth = 6,
177    FpDqDeqWidth = 6,
178    LsDqDeqWidth = 6,
179  ),
180  intPreg: PregParams = IntPregParams(
181    numEntries = 224,
182    numRead = None,
183    numWrite = None,
184  ),
185  vfPreg: VfPregParams = VfPregParams(
186    numEntries = 192,
187    numRead = Some(14),
188    numWrite = None,
189  ),
190  prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
191  LoadPipelineWidth: Int = 3,
192  StorePipelineWidth: Int = 2,
193  VecLoadPipelineWidth: Int = 2,
194  VecStorePipelineWidth: Int = 2,
195  VecMemSrcInWidth: Int = 2,
196  VecMemInstWbWidth: Int = 1,
197  VecMemDispatchWidth: Int = 1,
198  StoreBufferSize: Int = 16,
199  StoreBufferThreshold: Int = 7,
200  EnsbufferWidth: Int = 2,
201  // ============ VLSU ============
202  UsQueueSize: Int = 8,
203  VlFlowSize: Int = 32,
204  VlUopSize: Int = 32,
205  VsFlowSize: Int = 32,
206  VsUopSize: Int = 32,
207  // ==============================
208  UncacheBufferSize: Int = 4,
209  EnableLoadToLoadForward: Boolean = true,
210  EnableFastForward: Boolean = true,
211  EnableLdVioCheckAfterReset: Boolean = true,
212  EnableSoftPrefetchAfterReset: Boolean = true,
213  EnableCacheErrorAfterReset: Boolean = true,
214  EnableAccurateLoadError: Boolean = true,
215  EnableUncacheWriteOutstanding: Boolean = false,
216  EnableStorePrefetchAtIssue: Boolean = false,
217  EnableStorePrefetchAtCommit: Boolean = false,
218  EnableAtCommitMissTrigger: Boolean = true,
219  EnableStorePrefetchSMS: Boolean = false,
220  EnableStorePrefetchSPB: Boolean = false,
221  MMUAsidLen: Int = 16, // max is 16, 0 is not supported now
222  ReSelectLen: Int = 7, // load replay queue replay select counter len
223  iwpuParameters: WPUParameters = WPUParameters(
224    enWPU = false,
225    algoName = "mmru",
226    isICache = true,
227  ),
228  dwpuParameters: WPUParameters = WPUParameters(
229    enWPU = false,
230    algoName = "mmru",
231    enCfPred = false,
232    isICache = false,
233  ),
234  itlbParameters: TLBParameters = TLBParameters(
235    name = "itlb",
236    fetchi = true,
237    useDmode = false,
238    NWays = 48,
239  ),
240  itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1,
241  ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1,
242  ldtlbParameters: TLBParameters = TLBParameters(
243    name = "ldtlb",
244    NWays = 48,
245    outReplace = false,
246    partialStaticPMP = true,
247    outsideRecvFlush = true,
248    saveLevel = true
249  ),
250  sttlbParameters: TLBParameters = TLBParameters(
251    name = "sttlb",
252    NWays = 48,
253    outReplace = false,
254    partialStaticPMP = true,
255    outsideRecvFlush = true,
256    saveLevel = true
257  ),
258  hytlbParameters: TLBParameters = TLBParameters(
259    name = "hytlb",
260    NWays = 4,
261    partialStaticPMP = true,
262    outsideRecvFlush = true,
263    outReplace = false
264  ),
265  pftlbParameters: TLBParameters = TLBParameters(
266    name = "pftlb",
267    NWays = 48,
268    outReplace = false,
269    partialStaticPMP = true,
270    outsideRecvFlush = true,
271    saveLevel = true
272  ),
273  refillBothTlb: Boolean = false,
274  btlbParameters: TLBParameters = TLBParameters(
275    name = "btlb",
276    NWays = 48,
277  ),
278  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
279  NumPerfCounters: Int = 16,
280  icacheParameters: ICacheParameters = ICacheParameters(
281    tagECC = Some("parity"),
282    dataECC = Some("parity"),
283    replacer = Some("setplru"),
284    nMissEntries = 2,
285    nProbeEntries = 2,
286    nPrefetchEntries = 12,
287    nPrefBufferEntries = 32,
288  ),
289  dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
290    tagECC = Some("secded"),
291    dataECC = Some("secded"),
292    replacer = Some("setplru"),
293    nMissEntries = 16,
294    nProbeEntries = 8,
295    nReleaseEntries = 18,
296    nMaxPrefetchEntry = 6,
297  )),
298  L2CacheParamsOpt: Option[L2Param] = Some(L2Param(
299    name = "l2",
300    ways = 8,
301    sets = 1024, // default 512KB L2
302    prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams())
303  )),
304  L2NBanks: Int = 1,
305  usePTWRepeater: Boolean = false,
306  softTLB: Boolean = false, // dpi-c l1tlb debug only
307  softPTW: Boolean = false, // dpi-c l2tlb debug only
308  softPTWDelay: Int = 1
309){
310  def vlWidth = log2Up(VLEN) + 1
311
312  val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
313  val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
314
315  val intSchdParams = {
316    implicit val schdType: SchedulerType = IntScheduler()
317    SchdBlockParams(Seq(
318      IssueBlockParams(Seq(
319        ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))),
320        ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))),
321      ), numEntries = IssueQueueSize, numEnq = 2),
322      IssueBlockParams(Seq(
323        ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))),
324        ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))),
325      ), numEntries = IssueQueueSize, numEnq = 2),
326      IssueBlockParams(Seq(
327        ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))),
328        ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))),
329      ), numEntries = IssueQueueSize, numEnq = 2),
330      IssueBlockParams(Seq(
331        ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))),
332      ), numEntries = IssueQueueSize / 2, numEnq = 1),
333      IssueBlockParams(Seq(
334        ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(2, 0)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))),
335        ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))),
336      ), numEntries = IssueQueueSize, numEnq = 2),
337    ),
338      numPregs = intPreg.numEntries,
339      numDeqOutside = 0,
340      schdType = schdType,
341      rfDataWidth = intPreg.dataCfg.dataWidth,
342      numUopIn = dpParams.IntDqDeqWidth,
343    )
344  }
345  val vfSchdParams = {
346    implicit val schdType: SchedulerType = VfScheduler()
347    SchdBlockParams(Seq(
348      IssueBlockParams(Seq(
349        ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
350        ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))),
351      ), numEntries = IssueQueueSize, numEnq = 2),
352      IssueBlockParams(Seq(
353        ExeUnitParams("VFEX2", Seq(VfdivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))),
354      ), numEntries = IssueQueueSize, numEnq = 2),
355    ),
356      numPregs = vfPreg.numEntries,
357      numDeqOutside = 0,
358      schdType = schdType,
359      rfDataWidth = vfPreg.dataCfg.dataWidth,
360      numUopIn = dpParams.FpDqDeqWidth,
361    )
362  }
363
364  val memSchdParams = {
365    implicit val schdType: SchedulerType = MemScheduler()
366    val rfDataWidth = 64
367
368    SchdBlockParams(Seq(
369      IssueBlockParams(Seq(
370        ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(3, 0)), Seq(Seq(IntRD(12, 0)))),
371        ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))),
372      ), numEntries = IssueQueueSize, numEnq = 2),
373      IssueBlockParams(Seq(
374        ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))),
375        ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port
376      ), numEntries = IssueQueueSize, numEnq = 2),
377      IssueBlockParams(Seq(
378        ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(4, 0)), Seq(Seq(IntRD(13, 0)))),
379      ), numEntries = IssueQueueSize, numEnq = 2),
380      IssueBlockParams(Seq(
381        ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 1)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
382      ), numEntries = IssueQueueSize, numEnq = 2),
383      IssueBlockParams(Seq(
384        ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(12, Int.MaxValue)))),
385        ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))),
386      ), numEntries = IssueQueueSize, numEnq = 4),
387    ),
388      numPregs = intPreg.numEntries max vfPreg.numEntries,
389      numDeqOutside = 0,
390      schdType = schdType,
391      rfDataWidth = rfDataWidth,
392      numUopIn = dpParams.LsDqDeqWidth,
393    )
394  }
395
396  def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth
397
398  def iqWakeUpParams = {
399    Seq(
400      WakeUpConfig(
401        Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "LDU0", "LDU1", "HYU0") ->
402        Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0")
403      ),
404      WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0")),
405    ).flatten
406  }
407
408  def backendParams: BackendParams = backend.BackendParams(
409    Map(
410      IntScheduler() -> intSchdParams,
411      VfScheduler() -> vfSchdParams,
412      MemScheduler() -> memSchdParams,
413    ),
414    Seq(
415      intPreg,
416      vfPreg,
417    ),
418    iqWakeUpParams,
419  )
420}
421
422case object DebugOptionsKey extends Field[DebugOptions]
423
424case class DebugOptions
425(
426  FPGAPlatform: Boolean = false,
427  EnableDifftest: Boolean = false,
428  AlwaysBasicDiff: Boolean = true,
429  EnableDebug: Boolean = false,
430  EnablePerfDebug: Boolean = true,
431  UseDRAMSim: Boolean = false,
432  EnableConstantin: Boolean = false,
433  EnableChiselDB: Boolean = false,
434  AlwaysBasicDB: Boolean = true,
435  EnableTopDown: Boolean = false,
436  EnableRollingDB: Boolean = false
437)
438
439trait HasXSParameter {
440
441  implicit val p: Parameters
442
443  val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits
444
445  val coreParams = p(XSCoreParamsKey)
446  val env = p(DebugOptionsKey)
447
448  val XLEN = coreParams.XLEN
449  val VLEN = coreParams.VLEN
450  val ELEN = coreParams.ELEN
451  val minFLen = 32
452  val fLen = 64
453  def xLen = XLEN
454
455  val HasMExtension = coreParams.HasMExtension
456  val HasCExtension = coreParams.HasCExtension
457  val HasDiv = coreParams.HasDiv
458  val HasIcache = coreParams.HasICache
459  val HasDcache = coreParams.HasDCache
460  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
461  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
462  val AsidLength = coreParams.AsidLength
463  val ReSelectLen = coreParams.ReSelectLen
464  val AddrBytes = AddrBits / 8 // unused
465  val DataBits = XLEN
466  val DataBytes = DataBits / 8
467  val VDataBytes = VLEN / 8
468  val HasFPU = coreParams.HasFPU
469  val HasVPU = coreParams.HasVPU
470  val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp
471  val FetchWidth = coreParams.FetchWidth
472  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
473  val EnableBPU = coreParams.EnableBPU
474  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
475  val EnableRAS = coreParams.EnableRAS
476  val EnableLB = coreParams.EnableLB
477  val EnableLoop = coreParams.EnableLoop
478  val EnableSC = coreParams.EnableSC
479  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
480  val HistoryLength = coreParams.HistoryLength
481  val EnableGHistDiff = coreParams.EnableGHistDiff
482  val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff
483  val UbtbGHRLength = coreParams.UbtbGHRLength
484  val UbtbSize = coreParams.UbtbSize
485  val EnableFauFTB = coreParams.EnableFauFTB
486  val FtbSize = coreParams.FtbSize
487  val FtbWays = coreParams.FtbWays
488  val RasSize = coreParams.RasSize
489  val RasSpecSize = coreParams.RasSpecSize
490  val RasCtrSize = coreParams.RasCtrSize
491
492  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = {
493    coreParams.branchPredictor(resp_in, p)
494  }
495  val numBr = coreParams.numBr
496  val TageTableInfos = coreParams.TageTableInfos
497  val TageBanks = coreParams.numBr
498  val SCNRows = coreParams.SCNRows
499  val SCCtrBits = coreParams.SCCtrBits
500  val SCHistLens = coreParams.SCHistLens
501  val SCNTables = coreParams.SCNTables
502
503  val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map {
504    case ((n, cb), h) => (n, cb, h)
505  }
506  val ITTageTableInfos = coreParams.ITTageTableInfos
507  type FoldedHistoryInfo = Tuple2[Int, Int]
508  val foldedGHistInfos =
509    (TageTableInfos.map{ case (nRows, h, t) =>
510      if (h > 0)
511        Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1)))
512      else
513        Set[FoldedHistoryInfo]()
514    }.reduce(_++_).toSet ++
515    SCTableInfos.map{ case (nRows, _, h) =>
516      if (h > 0)
517        Set((h, min(log2Ceil(nRows/TageBanks), h)))
518      else
519        Set[FoldedHistoryInfo]()
520    }.reduce(_++_).toSet ++
521    ITTageTableInfos.map{ case (nRows, h, t) =>
522      if (h > 0)
523        Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1)))
524      else
525        Set[FoldedHistoryInfo]()
526    }.reduce(_++_) ++
527      Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize)))
528    ).toList
529
530
531
532  val CacheLineSize = coreParams.CacheLineSize
533  val CacheLineHalfWord = CacheLineSize / 16
534  val ExtHistoryLength = HistoryLength + 64
535  val IBufSize = coreParams.IBufSize
536  val DecodeWidth = coreParams.DecodeWidth
537  val RenameWidth = coreParams.RenameWidth
538  val CommitWidth = coreParams.CommitWidth
539  val MaxUopSize = coreParams.MaxUopSize
540  val EnableRenameSnapshot = coreParams.EnableRenameSnapshot
541  val RenameSnapshotNum = coreParams.RenameSnapshotNum
542  val FtqSize = coreParams.FtqSize
543  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
544  val IntLogicRegs = coreParams.IntLogicRegs
545  val FpLogicRegs = coreParams.FpLogicRegs
546  val VecLogicRegs = coreParams.VecLogicRegs
547  val VCONFIG_IDX = coreParams.VCONFIG_IDX
548  val IntPhyRegs = coreParams.intPreg.numEntries
549  val VfPhyRegs = coreParams.vfPreg.numEntries
550  val MaxPhyPregs = IntPhyRegs max VfPhyRegs
551  val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs)
552  val RobSize = coreParams.RobSize
553  val RabSize = coreParams.RabSize
554  val IntRefCounterWidth = log2Ceil(RobSize)
555  val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth
556  val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize
557  val LoadQueueRARSize = coreParams.LoadQueueRARSize
558  val LoadQueueRAWSize = coreParams.LoadQueueRAWSize
559  val RollbackGroupSize = coreParams.RollbackGroupSize
560  val LoadQueueReplaySize = coreParams.LoadQueueReplaySize
561  val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize
562  val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks
563  val StoreQueueSize = coreParams.StoreQueueSize
564  val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks
565  val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask
566  val VlsQueueSize = coreParams.VlsQueueSize
567  val dpParams = coreParams.dpParams
568
569  def backendParams: BackendParams = coreParams.backendParams
570  def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max
571  def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max
572
573  val NumRedirect = backendParams.numRedirect
574  val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception
575  val LoadPipelineWidth = coreParams.LoadPipelineWidth
576  val StorePipelineWidth = coreParams.StorePipelineWidth
577  val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth
578  val VecStorePipelineWidth = coreParams.VecStorePipelineWidth
579  val VecMemSrcInWidth = coreParams.VecMemSrcInWidth
580  val VecMemInstWbWidth = coreParams.VecMemInstWbWidth
581  val VecMemDispatchWidth = coreParams.VecMemDispatchWidth
582  val StoreBufferSize = coreParams.StoreBufferSize
583  val StoreBufferThreshold = coreParams.StoreBufferThreshold
584  val EnsbufferWidth = coreParams.EnsbufferWidth
585  val UsQueueSize = coreParams.UsQueueSize
586  val VlFlowSize = coreParams.VlFlowSize
587  val VlUopSize = coreParams.VlUopSize
588  val VsFlowSize = coreParams.VsFlowSize
589  val VsUopSize = coreParams.VsUopSize
590  val UncacheBufferSize = coreParams.UncacheBufferSize
591  val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward
592  val EnableFastForward = coreParams.EnableFastForward
593  val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset
594  val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset
595  val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset
596  val EnableAccurateLoadError = coreParams.EnableAccurateLoadError
597  val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding
598  val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue
599  val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit
600  val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger
601  val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS
602  val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB
603  val asidLen = coreParams.MMUAsidLen
604  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
605  val refillBothTlb = coreParams.refillBothTlb
606  val iwpuParam = coreParams.iwpuParameters
607  val dwpuParam = coreParams.dwpuParameters
608  val itlbParams = coreParams.itlbParameters
609  val ldtlbParams = coreParams.ldtlbParameters
610  val sttlbParams = coreParams.sttlbParameters
611  val hytlbParams = coreParams.hytlbParameters
612  val pftlbParams = coreParams.pftlbParameters
613  val btlbParams = coreParams.btlbParameters
614  val l2tlbParams = coreParams.l2tlbParameters
615  val NumPerfCounters = coreParams.NumPerfCounters
616
617  val instBytes = if (HasCExtension) 2 else 4
618  val instOffsetBits = log2Ceil(instBytes)
619
620  val icacheParameters = coreParams.icacheParameters
621  val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
622
623  // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles
624  // for constrained LR/SC loop
625  val LRSCCycles = 64
626  // for lr storm
627  val LRSCBackOff = 8
628
629  // cache hierarchy configurations
630  val l1BusDataWidth = 256
631
632  // load violation predict
633  val ResetTimeMax2Pow = 20 //1078576
634  val ResetTimeMin2Pow = 10 //1024
635  // wait table parameters
636  val WaitTableSize = 1024
637  val MemPredPCWidth = log2Up(WaitTableSize)
638  val LWTUse2BitCounter = true
639  // store set parameters
640  val SSITSize = WaitTableSize
641  val LFSTSize = 32
642  val SSIDWidth = log2Up(LFSTSize)
643  val LFSTWidth = 4
644  val StoreSetEnable = true // LWT will be disabled if SS is enabled
645  val LFSTEnable = false
646
647  val PCntIncrStep: Int = 6
648  val numPCntHc: Int = 25
649  val numPCntPtw: Int = 19
650
651  val numCSRPCntFrontend = 8
652  val numCSRPCntCtrl     = 8
653  val numCSRPCntLsu      = 8
654  val numCSRPCntHc       = 5
655}
656