1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 RasSpecSize: Int = 64, 91 RasCtrSize: Int = 8, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 IBufSize: Int = 48, 145 DecodeWidth: Int = 6, 146 RenameWidth: Int = 6, 147 CommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 33, 155 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 156 VCONFIG_IDX: Int = 32, 157 NRPhyRegs: Int = 192, 158 VirtualLoadQueueSize: Int = 80, 159 LoadQueueRARSize: Int = 80, 160 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 161 RollbackGroupSize: Int = 8, 162 LoadQueueReplaySize: Int = 72, 163 LoadUncacheBufferSize: Int = 20, 164 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 165 StoreQueueSize: Int = 64, 166 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 167 StoreQueueForwardWithMask: Boolean = true, 168 VlsQueueSize: Int = 8, 169 RobSize: Int = 256, 170 RabSize: Int = 256, 171 IssueQueueSize: Int = 32, 172 dpParams: DispatchParameters = DispatchParameters( 173 IntDqSize = 16, 174 FpDqSize = 16, 175 LsDqSize = 18, 176 IntDqDeqWidth = 6, 177 FpDqDeqWidth = 6, 178 LsDqDeqWidth = 6, 179 ), 180 intPreg: PregParams = IntPregParams( 181 numEntries = 224, 182 numRead = None, 183 numWrite = None, 184 ), 185 vfPreg: VfPregParams = VfPregParams( 186 numEntries = 192, 187 numRead = None, 188 numWrite = None, 189 ), 190 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 191 LoadPipelineWidth: Int = 3, 192 StorePipelineWidth: Int = 2, 193 VecMemSrcInWidth: Int = 2, 194 VecMemInstWbWidth: Int = 1, 195 VecMemDispatchWidth: Int = 1, 196 StoreBufferSize: Int = 16, 197 StoreBufferThreshold: Int = 7, 198 EnsbufferWidth: Int = 2, 199 UncacheBufferSize: Int = 4, 200 EnableLoadToLoadForward: Boolean = true, 201 EnableFastForward: Boolean = true, 202 EnableLdVioCheckAfterReset: Boolean = true, 203 EnableSoftPrefetchAfterReset: Boolean = true, 204 EnableCacheErrorAfterReset: Boolean = true, 205 EnableAccurateLoadError: Boolean = true, 206 EnableUncacheWriteOutstanding: Boolean = false, 207 EnableStorePrefetchAtIssue: Boolean = false, 208 EnableStorePrefetchAtCommit: Boolean = false, 209 EnableAtCommitMissTrigger: Boolean = true, 210 EnableStorePrefetchSMS: Boolean = false, 211 EnableStorePrefetchSPB: Boolean = false, 212 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 213 ReSelectLen: Int = 7, // load replay queue replay select counter len 214 iwpuParameters: WPUParameters = WPUParameters( 215 enWPU = false, 216 algoName = "mmru", 217 isICache = true, 218 ), 219 dwpuParameters: WPUParameters = WPUParameters( 220 enWPU = false, 221 algoName = "mmru", 222 enCfPred = false, 223 isICache = false, 224 ), 225 itlbParameters: TLBParameters = TLBParameters( 226 name = "itlb", 227 fetchi = true, 228 useDmode = false, 229 NWays = 48, 230 ), 231 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 232 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 233 ldtlbParameters: TLBParameters = TLBParameters( 234 name = "ldtlb", 235 NWays = 48, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 sttlbParameters: TLBParameters = TLBParameters( 242 name = "sttlb", 243 NWays = 48, 244 outReplace = false, 245 partialStaticPMP = true, 246 outsideRecvFlush = true, 247 saveLevel = true 248 ), 249 hytlbParameters: TLBParameters = TLBParameters( 250 name = "hytlb", 251 NWays = 4, 252 partialStaticPMP = true, 253 outsideRecvFlush = true, 254 outReplace = false 255 ), 256 pftlbParameters: TLBParameters = TLBParameters( 257 name = "pftlb", 258 NWays = 48, 259 outReplace = false, 260 partialStaticPMP = true, 261 outsideRecvFlush = true, 262 saveLevel = true 263 ), 264 refillBothTlb: Boolean = false, 265 btlbParameters: TLBParameters = TLBParameters( 266 name = "btlb", 267 NWays = 48, 268 ), 269 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 270 NumPerfCounters: Int = 16, 271 icacheParameters: ICacheParameters = ICacheParameters( 272 tagECC = Some("parity"), 273 dataECC = Some("parity"), 274 replacer = Some("setplru"), 275 nMissEntries = 2, 276 nProbeEntries = 2, 277 nPrefetchEntries = 12, 278 nPrefBufferEntries = 32, 279 ), 280 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 281 tagECC = Some("secded"), 282 dataECC = Some("secded"), 283 replacer = Some("setplru"), 284 nMissEntries = 16, 285 nProbeEntries = 8, 286 nReleaseEntries = 18, 287 nMaxPrefetchEntry = 6, 288 )), 289 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 290 name = "l2", 291 ways = 8, 292 sets = 1024, // default 512KB L2 293 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 294 )), 295 L2NBanks: Int = 1, 296 usePTWRepeater: Boolean = false, 297 softTLB: Boolean = false, // dpi-c l1tlb debug only 298 softPTW: Boolean = false, // dpi-c l2tlb debug only 299 softPTWDelay: Int = 1 300){ 301 def vlWidth = log2Up(VLEN) + 1 302 303 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 304 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 305 306 val intSchdParams = { 307 implicit val schdType: SchedulerType = IntScheduler() 308 SchdBlockParams(Seq( 309 IssueBlockParams(Seq( 310 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 311 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 312 ), numEntries = IssueQueueSize, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 315 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 316 ), numEntries = IssueQueueSize, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 319 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))), 320 ), numEntries = IssueQueueSize, numEnq = 2), 321 IssueBlockParams(Seq( 322 ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(15, 0)))), 323 ), numEntries = IssueQueueSize / 2, numEnq = 1), 324 IssueBlockParams(Seq( 325 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(2, 0)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))), 326 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))), 327 ), numEntries = IssueQueueSize, numEnq = 2), 328 ), 329 numPregs = intPreg.numEntries, 330 numDeqOutside = 0, 331 schdType = schdType, 332 rfDataWidth = intPreg.dataCfg.dataWidth, 333 numUopIn = dpParams.IntDqDeqWidth, 334 ) 335 } 336 val vfSchdParams = { 337 implicit val schdType: SchedulerType = VfScheduler() 338 SchdBlockParams(Seq( 339 IssueBlockParams(Seq( 340 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 341 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 342 ), numEntries = IssueQueueSize, numEnq = 2), 343 IssueBlockParams(Seq( 344 ExeUnitParams("VFEX2", Seq(VfdivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 345 ), numEntries = IssueQueueSize, numEnq = 2), 346 ), 347 numPregs = vfPreg.numEntries, 348 numDeqOutside = 0, 349 schdType = schdType, 350 rfDataWidth = vfPreg.dataCfg.dataWidth, 351 numUopIn = dpParams.FpDqDeqWidth, 352 ) 353 } 354 355 val memSchdParams = { 356 implicit val schdType: SchedulerType = MemScheduler() 357 val rfDataWidth = 64 358 359 SchdBlockParams(Seq( 360 IssueBlockParams(Seq( 361 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(3, 0)), Seq(Seq(IntRD(12, 0)))), 362 ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))), 363 ), numEntries = IssueQueueSize, numEnq = 2), 364 IssueBlockParams(Seq( 365 ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))), 366 ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port 367 ), numEntries = IssueQueueSize, numEnq = 2), 368 IssueBlockParams(Seq( 369 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(4, 0)), Seq(Seq(IntRD(13, 0)))), 370 ), numEntries = IssueQueueSize, numEnq = 2), 371 IssueBlockParams(Seq( 372 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(3, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 373 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(4, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 374 ), numEntries = IssueQueueSize, numEnq = 2), 375 IssueBlockParams(Seq( 376 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(12, Int.MaxValue)))), 377 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))), 378 ), numEntries = IssueQueueSize, numEnq = 4), 379 ), 380 numPregs = intPreg.numEntries max vfPreg.numEntries, 381 numDeqOutside = 0, 382 schdType = schdType, 383 rfDataWidth = rfDataWidth, 384 numUopIn = dpParams.LsDqDeqWidth, 385 ) 386 } 387 388 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 389 390 def iqWakeUpParams = { 391 Seq( 392 WakeUpConfig( 393 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "LDU0", "LDU1", "HYU0") -> 394 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0") 395 ), 396 WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0")), 397 ).flatten 398 } 399 400 def backendParams: BackendParams = backend.BackendParams( 401 Map( 402 IntScheduler() -> intSchdParams, 403 VfScheduler() -> vfSchdParams, 404 MemScheduler() -> memSchdParams, 405 ), 406 Seq( 407 intPreg, 408 vfPreg, 409 ), 410 iqWakeUpParams, 411 ) 412} 413 414case object DebugOptionsKey extends Field[DebugOptions] 415 416case class DebugOptions 417( 418 FPGAPlatform: Boolean = false, 419 EnableDifftest: Boolean = false, 420 AlwaysBasicDiff: Boolean = true, 421 EnableDebug: Boolean = false, 422 EnablePerfDebug: Boolean = true, 423 UseDRAMSim: Boolean = false, 424 EnableConstantin: Boolean = false, 425 EnableChiselDB: Boolean = false, 426 AlwaysBasicDB: Boolean = true, 427 EnableTopDown: Boolean = false, 428 EnableRollingDB: Boolean = false 429) 430 431trait HasXSParameter { 432 433 implicit val p: Parameters 434 435 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 436 437 val coreParams = p(XSCoreParamsKey) 438 val env = p(DebugOptionsKey) 439 440 val XLEN = coreParams.XLEN 441 val VLEN = coreParams.VLEN 442 val ELEN = coreParams.ELEN 443 val minFLen = 32 444 val fLen = 64 445 def xLen = XLEN 446 447 val HasMExtension = coreParams.HasMExtension 448 val HasCExtension = coreParams.HasCExtension 449 val HasDiv = coreParams.HasDiv 450 val HasIcache = coreParams.HasICache 451 val HasDcache = coreParams.HasDCache 452 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 453 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 454 val AsidLength = coreParams.AsidLength 455 val ReSelectLen = coreParams.ReSelectLen 456 val AddrBytes = AddrBits / 8 // unused 457 val DataBits = XLEN 458 val DataBytes = DataBits / 8 459 val VDataBytes = VLEN / 8 460 val HasFPU = coreParams.HasFPU 461 val HasVPU = coreParams.HasVPU 462 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 463 val FetchWidth = coreParams.FetchWidth 464 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 465 val EnableBPU = coreParams.EnableBPU 466 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 467 val EnableRAS = coreParams.EnableRAS 468 val EnableLB = coreParams.EnableLB 469 val EnableLoop = coreParams.EnableLoop 470 val EnableSC = coreParams.EnableSC 471 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 472 val HistoryLength = coreParams.HistoryLength 473 val EnableGHistDiff = coreParams.EnableGHistDiff 474 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 475 val UbtbGHRLength = coreParams.UbtbGHRLength 476 val UbtbSize = coreParams.UbtbSize 477 val EnableFauFTB = coreParams.EnableFauFTB 478 val FtbSize = coreParams.FtbSize 479 val FtbWays = coreParams.FtbWays 480 val RasSize = coreParams.RasSize 481 val RasSpecSize = coreParams.RasSpecSize 482 val RasCtrSize = coreParams.RasCtrSize 483 484 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 485 coreParams.branchPredictor(resp_in, p) 486 } 487 val numBr = coreParams.numBr 488 val TageTableInfos = coreParams.TageTableInfos 489 val TageBanks = coreParams.numBr 490 val SCNRows = coreParams.SCNRows 491 val SCCtrBits = coreParams.SCCtrBits 492 val SCHistLens = coreParams.SCHistLens 493 val SCNTables = coreParams.SCNTables 494 495 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 496 case ((n, cb), h) => (n, cb, h) 497 } 498 val ITTageTableInfos = coreParams.ITTageTableInfos 499 type FoldedHistoryInfo = Tuple2[Int, Int] 500 val foldedGHistInfos = 501 (TageTableInfos.map{ case (nRows, h, t) => 502 if (h > 0) 503 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 504 else 505 Set[FoldedHistoryInfo]() 506 }.reduce(_++_).toSet ++ 507 SCTableInfos.map{ case (nRows, _, h) => 508 if (h > 0) 509 Set((h, min(log2Ceil(nRows/TageBanks), h))) 510 else 511 Set[FoldedHistoryInfo]() 512 }.reduce(_++_).toSet ++ 513 ITTageTableInfos.map{ case (nRows, h, t) => 514 if (h > 0) 515 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 516 else 517 Set[FoldedHistoryInfo]() 518 }.reduce(_++_) ++ 519 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 520 ).toList 521 522 523 524 val CacheLineSize = coreParams.CacheLineSize 525 val CacheLineHalfWord = CacheLineSize / 16 526 val ExtHistoryLength = HistoryLength + 64 527 val IBufSize = coreParams.IBufSize 528 val DecodeWidth = coreParams.DecodeWidth 529 val RenameWidth = coreParams.RenameWidth 530 val CommitWidth = coreParams.CommitWidth 531 val MaxUopSize = coreParams.MaxUopSize 532 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 533 val RenameSnapshotNum = coreParams.RenameSnapshotNum 534 val FtqSize = coreParams.FtqSize 535 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 536 val IntLogicRegs = coreParams.IntLogicRegs 537 val FpLogicRegs = coreParams.FpLogicRegs 538 val VecLogicRegs = coreParams.VecLogicRegs 539 val VCONFIG_IDX = coreParams.VCONFIG_IDX 540 val IntPhyRegs = coreParams.intPreg.numEntries 541 val VfPhyRegs = coreParams.vfPreg.numEntries 542 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 543 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 544 val RobSize = coreParams.RobSize 545 val RabSize = coreParams.RabSize 546 val IntRefCounterWidth = log2Ceil(RobSize) 547 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 548 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 549 val LoadQueueRARSize = coreParams.LoadQueueRARSize 550 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 551 val RollbackGroupSize = coreParams.RollbackGroupSize 552 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 553 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 554 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 555 val StoreQueueSize = coreParams.StoreQueueSize 556 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 557 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 558 val VlsQueueSize = coreParams.VlsQueueSize 559 val dpParams = coreParams.dpParams 560 561 def backendParams: BackendParams = coreParams.backendParams 562 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 563 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 564 565 val NumRedirect = backendParams.numRedirect 566 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 567 val LoadPipelineWidth = coreParams.LoadPipelineWidth 568 val StorePipelineWidth = coreParams.StorePipelineWidth 569 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 570 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 571 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 572 val StoreBufferSize = coreParams.StoreBufferSize 573 val StoreBufferThreshold = coreParams.StoreBufferThreshold 574 val EnsbufferWidth = coreParams.EnsbufferWidth 575 val UncacheBufferSize = coreParams.UncacheBufferSize 576 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 577 val EnableFastForward = coreParams.EnableFastForward 578 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 579 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 580 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 581 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 582 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 583 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 584 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 585 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 586 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 587 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 588 val asidLen = coreParams.MMUAsidLen 589 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 590 val refillBothTlb = coreParams.refillBothTlb 591 val iwpuParam = coreParams.iwpuParameters 592 val dwpuParam = coreParams.dwpuParameters 593 val itlbParams = coreParams.itlbParameters 594 val ldtlbParams = coreParams.ldtlbParameters 595 val sttlbParams = coreParams.sttlbParameters 596 val hytlbParams = coreParams.hytlbParameters 597 val pftlbParams = coreParams.pftlbParameters 598 val btlbParams = coreParams.btlbParameters 599 val l2tlbParams = coreParams.l2tlbParameters 600 val NumPerfCounters = coreParams.NumPerfCounters 601 602 val instBytes = if (HasCExtension) 2 else 4 603 val instOffsetBits = log2Ceil(instBytes) 604 605 val icacheParameters = coreParams.icacheParameters 606 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 607 608 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 609 // for constrained LR/SC loop 610 val LRSCCycles = 64 611 // for lr storm 612 val LRSCBackOff = 8 613 614 // cache hierarchy configurations 615 val l1BusDataWidth = 256 616 617 // load violation predict 618 val ResetTimeMax2Pow = 20 //1078576 619 val ResetTimeMin2Pow = 10 //1024 620 // wait table parameters 621 val WaitTableSize = 1024 622 val MemPredPCWidth = log2Up(WaitTableSize) 623 val LWTUse2BitCounter = true 624 // store set parameters 625 val SSITSize = WaitTableSize 626 val LFSTSize = 32 627 val SSIDWidth = log2Up(LFSTSize) 628 val LFSTWidth = 4 629 val StoreSetEnable = true // LWT will be disabled if SS is enabled 630 val LFSTEnable = false 631 632 val PCntIncrStep: Int = 6 633 val numPCntHc: Int = 25 634 val numPCntPtw: Int = 19 635 636 val numCSRPCntFrontend = 8 637 val numCSRPCntCtrl = 8 638 val numCSRPCntLsu = 8 639 val numCSRPCntHc = 5 640} 641