| #
441ad0cd |
| 19-Nov-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into fix-module-level
|
| #
c7658a75 |
| 18-Nov-2020 |
Yinan Xu <[email protected]> |
lsq: remove seperated lsroq
|
| #
1c2588aa |
| 18-Nov-2020 |
Yinan Xu <[email protected]> |
XSCore: use Blocks
|
| #
6b98bdcb |
| 18-Nov-2020 |
Lingrui98 <[email protected]> |
SC: yet to debug
|
| #
ccce3504 |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/fix-module-level' into fp-recodeFN
|
| #
9684eb4f |
| 15-Nov-2020 |
LinJiawei <[email protected]> |
EXU: spilt int data path and float data path
|
| #
caaba477 |
| 15-Nov-2020 |
Lingrui98 <[email protected]> |
Merge remote-tracking branch 'origin/master' into tage-sc
|
| #
534e17a9 |
| 10-Nov-2020 |
Lingrui98 <[email protected]> |
Bundle: use val for constructing method of SCMeta
|
| #
3c768696 |
| 09-Nov-2020 |
zoujr <[email protected]> |
Merge branch 'master' into new-lbuf
|
| #
77d8ca7c |
| 08-Nov-2020 |
Lingrui98 <[email protected]> |
merge master into tage-sc
|
| #
7eaf1071 |
| 06-Nov-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/fix-dispatch-replay' into xs-fpu
|
| #
be784967 |
| 05-Nov-2020 |
LinJiawei <[email protected]> |
Remove all boringutils except Regfile
|
| #
2fdc488a |
| 05-Nov-2020 |
LinJiawei <[email protected]> |
Remove BoringUtils in fence unit
|
| #
2fbdb79b |
| 04-Nov-2020 |
Lingrui98 <[email protected]> |
BPU: add statistical corrector, to be debugged
|
| #
ef74f7cb |
| 02-Nov-2020 |
LinJiawei <[email protected]> |
Merge remote-tracking branch 'origin/fix-boringutils' into xs-fpu
|
| #
3fa7b737 |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
roq,csr: only raiseInterrupt when roq redirects an interrupt
Previously, CSR determines interrupt by redirect.valid && interruptBitEnable.
However, interruptBitEnable does not mean the redirect is a
roq,csr: only raiseInterrupt when roq redirects an interrupt
Previously, CSR determines interrupt by redirect.valid && interruptBitEnable.
However, interruptBitEnable does not mean the redirect is an interrupt.
We reuse isFlushPipe in Roq to represent an interrupt for CSR.
show more ...
|
| #
8e8cb3b4 |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
xiangshan: remove noop code from repo
|
| #
35bfeecb |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
csr: use IO for mtip,msip,meip
|
| #
3136ee6a |
| 02-Nov-2020 |
LinJiawei <[email protected]> |
Merge 'master' into 'xs-fpu'
|
| #
11131ea4 |
| 01-Nov-2020 |
Yinan Xu <[email protected]> |
mem,lsq: remove excitingutils for exception vaddr
|
| #
65cacaf2 |
| 27-Oct-2020 |
zoujr <[email protected]> |
Merge branch 'master' into dev-lbuf
|
| #
9ac14628 |
| 27-Oct-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into perf-debug
|
| #
4fb541a1 |
| 25-Oct-2020 |
Yinan Xu <[email protected]> |
mem,lsq: remove instIsStore and use commitType instead
|
| #
5c1ae31b |
| 24-Oct-2020 |
Yinan Xu <[email protected]> |
StoreQueue: use SqPtr as queue pointer instead of raw UInt
Futher we will support store queue size that is not power of 2.
However, currently there're still bugs.
|
| #
915c0dd4 |
| 24-Oct-2020 |
Yinan Xu <[email protected]> |
LoadQueue: support size that is not power of 2
|