1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8import xiangshan.backend.roq.RoqPtr 9import xiangshan.mem.{LqPtr, SqPtr} 10import xiangshan.frontend.PreDecodeInfo 11import xiangshan.frontend.HasBPUParameter 12import xiangshan.frontend.HasTageParameter 13 14// Fetch FetchWidth x 32-bit insts from Icache 15class FetchPacket extends XSBundle { 16 val instrs = Vec(PredictWidth, UInt(32.W)) 17 val mask = UInt(PredictWidth.W) 18 // val pc = UInt(VAddrBits.W) 19 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 20 val pnpc = Vec(PredictWidth, UInt(VAddrBits.W)) 21 val brInfo = Vec(PredictWidth, new BranchInfo) 22 val pd = Vec(PredictWidth, new PreDecodeInfo) 23 val ipf = Bool() 24 val crossPageIPFFix = Bool() 25} 26 27class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 28 val valid = Bool() 29 val bits = gen.cloneType.asInstanceOf[T] 30 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 31} 32 33object ValidUndirectioned { 34 def apply[T <: Data](gen: T) = { 35 new ValidUndirectioned[T](gen) 36 } 37} 38 39class TageMeta extends XSBundle with HasTageParameter { 40 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 41 val altDiffers = Bool() 42 val providerU = UInt(2.W) 43 val providerCtr = UInt(3.W) 44 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 45} 46 47class BranchPrediction extends XSBundle { 48 val redirect = Bool() 49 val taken = Bool() 50 val jmpIdx = UInt(log2Up(PredictWidth).W) 51 val hasNotTakenBrs = Bool() 52 val target = UInt(VAddrBits.W) 53 val saveHalfRVI = Bool() 54 val takenOnBr = Bool() 55} 56 57class BranchInfo extends XSBundle with HasBPUParameter { 58 val ubtbWriteWay = UInt(log2Up(UBtbWays).W) 59 val ubtbHits = Bool() 60 val btbWriteWay = UInt(log2Up(BtbWays).W) 61 val btbHitJal = Bool() 62 val bimCtr = UInt(2.W) 63 val histPtr = UInt(log2Up(ExtHistoryLength).W) 64 val predHistPtr = UInt(log2Up(ExtHistoryLength).W) 65 val tageMeta = new TageMeta 66 val rasSp = UInt(log2Up(RasSize).W) 67 val rasTopCtr = UInt(8.W) 68 val rasToqAddr = UInt(VAddrBits.W) 69 val fetchIdx = UInt(log2Up(PredictWidth).W) 70 val specCnt = UInt(10.W) 71 val sawNotTakenBranch = Bool() 72 73 val debug_ubtb_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W) 74 val debug_btb_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W) 75 val debug_tage_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W) 76 77 def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = { 78 this.histPtr := histPtr 79 this.tageMeta := tageMeta 80 this.rasSp := rasSp 81 this.rasTopCtr := rasTopCtr 82 this.asUInt 83 } 84 def size = 0.U.asTypeOf(this).getWidth 85 def fromUInt(x: UInt) = x.asTypeOf(this) 86} 87 88class Predecode extends XSBundle { 89 val isFetchpcEqualFirstpc = Bool() 90 val mask = UInt((FetchWidth*2).W) 91 val pd = Vec(FetchWidth*2, (new PreDecodeInfo)) 92} 93 94class BranchUpdateInfo extends XSBundle { 95 // from backend 96 val pc = UInt(VAddrBits.W) 97 val pnpc = UInt(VAddrBits.W) 98 val target = UInt(VAddrBits.W) 99 val brTarget = UInt(VAddrBits.W) 100 val taken = Bool() 101 val fetchIdx = UInt(log2Up(FetchWidth*2).W) 102 val isMisPred = Bool() 103 val brTag = new BrqPtr 104 105 // frontend -> backend -> frontend 106 val pd = new PreDecodeInfo 107 val brInfo = new BranchInfo 108} 109 110// Dequeue DecodeWidth insts from Ibuffer 111class CtrlFlow extends XSBundle { 112 val instr = UInt(32.W) 113 val pc = UInt(VAddrBits.W) 114 val exceptionVec = Vec(16, Bool()) 115 val intrVec = Vec(12, Bool()) 116 val brUpdate = new BranchUpdateInfo 117 val crossPageIPFFix = Bool() 118} 119 120// Decode DecodeWidth insts at Decode Stage 121class CtrlSignals extends XSBundle { 122 val src1Type, src2Type, src3Type = SrcType() 123 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 124 val ldest = UInt(5.W) 125 val fuType = FuType() 126 val fuOpType = FuOpType() 127 val rfWen = Bool() 128 val fpWen = Bool() 129 val isXSTrap = Bool() 130 val noSpecExec = Bool() // This inst can not be speculated 131 val isBlocked = Bool() // This inst requires pipeline to be blocked 132 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 133 val isRVF = Bool() 134 val imm = UInt(XLEN.W) 135 val commitType = CommitType() 136} 137 138class CfCtrl extends XSBundle { 139 val cf = new CtrlFlow 140 val ctrl = new CtrlSignals 141 val brTag = new BrqPtr 142} 143 144// Load / Store Index 145// 146// When using unified lsroq, lsIdx serves as lsroqIdx, 147// while separated lq and sq is used, lsIdx consists of lqIdx, sqIdx and l/s type. 148// All lsroqIdx will be replaced by new lsIdx in the future. 149trait HasLSIdx { this: HasXSParameter => 150 151 // if(EnableUnifiedLSQ){ 152 // Unified LSQ 153 val lsroqIdx = UInt(LsroqIdxWidth.W) 154 // } else { 155 // Separate LSQ 156 val lqIdx = new LqPtr 157 val sqIdx = new SqPtr 158} 159 160class LSIdx extends XSBundle with HasLSIdx {} 161 162// CfCtrl -> MicroOp at Rename Stage 163class MicroOp extends CfCtrl with HasLSIdx { 164 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 165 val src1State, src2State, src3State = SrcState() 166 val roqIdx = new RoqPtr 167 val diffTestDebugLrScValid = Bool() 168} 169 170class Redirect extends XSBundle { 171 val roqIdx = new RoqPtr 172 val isException = Bool() 173 val isMisPred = Bool() 174 val isReplay = Bool() 175 val isFlushPipe = Bool() 176 val pc = UInt(VAddrBits.W) 177 val target = UInt(VAddrBits.W) 178 val brTag = new BrqPtr 179} 180 181class Dp1ToDp2IO extends XSBundle { 182 val intDqToDp2 = Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp)) 183 val fpDqToDp2 = Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp)) 184 val lsDqToDp2 = Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp)) 185} 186 187class ReplayPregReq extends XSBundle { 188 // NOTE: set isInt and isFp both to 'false' when invalid 189 val isInt = Bool() 190 val isFp = Bool() 191 val preg = UInt(PhyRegIdxWidth.W) 192} 193 194class DebugBundle extends XSBundle{ 195 val isMMIO = Bool() 196} 197 198class ExuInput extends XSBundle { 199 val uop = new MicroOp 200 val src1, src2, src3 = UInt(XLEN.W) 201} 202 203class ExuOutput extends XSBundle { 204 val uop = new MicroOp 205 val data = UInt(XLEN.W) 206 val redirectValid = Bool() 207 val redirect = new Redirect 208 val brUpdate = new BranchUpdateInfo 209 val debug = new DebugBundle 210} 211 212class ExuIO extends XSBundle { 213 val in = Flipped(DecoupledIO(new ExuInput)) 214 val redirect = Flipped(ValidIO(new Redirect)) 215 val out = DecoupledIO(new ExuOutput) 216 // for csr 217 val exception = Flipped(ValidIO(new MicroOp)) 218 // for Lsu 219 val dmem = new SimpleBusUC 220 val mcommit = Input(UInt(3.W)) 221} 222 223class RoqCommit extends XSBundle { 224 val uop = new MicroOp 225 val isWalk = Bool() 226} 227 228class TlbFeedback extends XSBundle { 229 val roqIdx = new RoqPtr 230 val hit = Bool() 231} 232 233class FrontendToBackendIO extends XSBundle { 234 // to backend end 235 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 236 // from backend 237 val redirect = Flipped(ValidIO(new Redirect)) 238 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 239 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 240} 241 242class TlbCsrBundle extends XSBundle { 243 val satp = new Bundle { 244 val mode = UInt(4.W) // TODO: may change number to parameter 245 val asid = UInt(16.W) 246 val ppn = UInt(44.W) // just use PAddrBits - 3 - vpnnLen 247 } 248 val priv = new Bundle { 249 val mxr = Bool() 250 val sum = Bool() 251 val imode = UInt(2.W) 252 val dmode = UInt(2.W) 253 } 254 255 override def toPrintable: Printable = { 256 p"Satp mode:0x${Hexadecimal(satp.mode)} asid:0x${Hexadecimal(satp.asid)} ppn:0x${Hexadecimal(satp.ppn)} " + 257 p"Priv mxr:${priv.mxr} sum:${priv.sum} imode:${priv.imode} dmode:${priv.dmode}" 258 } 259} 260 261class SfenceBundle extends XSBundle { 262 val valid = Bool() 263 val bits = new Bundle { 264 val rs1 = Bool() 265 val rs2 = Bool() 266 val addr = UInt(VAddrBits.W) 267 } 268 269 override def toPrintable: Printable = { 270 p"valid:0x${Hexadecimal(valid)} rs1:${bits.rs1} rs2:${bits.rs2} addr:${Hexadecimal(bits.addr)}" 271 } 272} 273