1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package futest 18 19import chisel3._ 20import chiseltest._ 21import chiseltest.ChiselScalatestTester 22import chiseltest.experimental.TestOptionBuilder._ 23import chiseltest.internal.{LineCoverageAnnotation, ToggleCoverageAnnotation, VerilatorBackendAnnotation} 24import chiseltest.legacy.backends.verilator.VerilatorFlags 25import org.scalatest.flatspec.AnyFlatSpec 26import org.scalatest.matchers.must.Matchers 27import firrtl.stage.RunFirrtlTransformAnnotation 28import xstransforms.PrintModuleName 29 30import xiangshan.backend.fu._ 31 32import scala.util.Random 33 34 35class SRT4DividerWrapper extends Module { 36 val io = IO(new Bundle{ 37 val dividend = Input(UInt(64.W)) 38 val divisor = Input(UInt(64.W)) 39 val sign = Input(Bool()) 40 val isHi = Input(Bool()) 41 val isW = Input(Bool()) 42 val in_valid = Input(Bool()) 43 val out_ready = Input(Bool()) 44 val in_ready = Output(Bool()) 45 val out_valid = Output(Bool()) 46 val result = Output(UInt(64.W)) 47 }) 48 val divider = Module(new SRT16DividerDataModule(len = 64)) 49 divider.io.src(0) := io.dividend 50 divider.io.src(1) := io.divisor 51 divider.io.kill_r := false.B 52 divider.io.kill_w := false.B 53 divider.io.sign := io.sign 54 divider.io.isHi := io.isHi 55 divider.io.isW := io.isW 56 divider.io.out_ready := io.out_ready 57 divider.io.valid := io.in_valid 58 59 io.in_ready := divider.io.in_ready 60 io.out_valid := divider.io.out_valid 61 62 io.result := divider.io.out_data 63 64} 65 66class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers { 67 behavior of "srt16 divider" 68 it should "run" in { 69 val rand = new Random(0x14226) 70 val testNum = 1000 71 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation, 72 LineCoverageAnnotation, 73 ToggleCoverageAnnotation, 74 VerilatorFlags(Seq("--output-split 5000", "--output-split-cfuncs 5000", 75 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")), 76 RunFirrtlTransformAnnotation(new PrintModuleName))){ m => 77 println("Test started!") 78 m.clock.step(20) 79 80 for (i <- 1 to testNum) { 81 m.clock.step(3) 82 m.io.in_ready.expect(true.B) 83 val divisor = rand.nextLong() 84 val dividend = rand.nextLong() 85 // val sign = rand.nextBoolean() 86 87 // val isSigned = if (sign) s"Signed division" else s"Unsigned division" 88 println(s"$i th iteration\n" + s"divisor is ${divisor.toHexString}, dividend is ${dividend.toHexString}") 89 m.io.in_valid.poke(true.B) 90 m.io.dividend.poke((s"b" + dividend.toBinaryString).asUInt(64.W)) 91 m.io.divisor.poke((s"b" + divisor.toBinaryString).asUInt(64.W)) 92 m.io.sign.poke(true.B) 93 val (quotient, remainder) = (dividend / divisor, dividend % divisor) 94 println(s"quotient is ${quotient.toHexString}, remainder is ${remainder.toHexString}") 95 var timeTaken = 0 96 while (m.io.out_valid.peek().litToBoolean != true) { 97 m.clock.step() 98 timeTaken += 1 99 if (timeTaken >= 62) assert(false, s"Timeout for single execution!!!") 100 } 101 102 m.io.in_valid.poke(false.B) 103 m.io.out_ready.poke(true.B) 104 m.io.isHi.poke(false.B) 105 m.clock.step() 106 107 m.io.result.expect((s"b" + quotient.toBinaryString).asUInt(64.W)) 108 m.io.isHi.poke(true.B) 109 m.clock.step() 110 111 m.io.result.expect((s"b" + remainder.toBinaryString).asUInt(64.W)) 112 } 113 } 114 } 115}