1/*************************************************************************************** 2 * Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3 * Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4 * Copyright (c) 2020-2021 Peng Cheng Laboratory 5 * 6 * XiangShan is licensed under Mulan PSL v2. 7 * You can use this software according to the terms and conditions of the Mulan PSL v2. 8 * You may obtain a copy of Mulan PSL v2 at: 9 * http://license.coscl.org.cn/MulanPSL2 10 * 11 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14 * 15 * See the Mulan PSL v2 for more details. 16 ***************************************************************************************/ 17 18package futest 19 20import chisel3._ 21import chiseltest._ 22import chiseltest.ChiselScalatestTester 23import chiseltest.VerilatorBackendAnnotation 24import chiseltest.simulator.VerilatorFlags 25import org.scalatest.flatspec.AnyFlatSpec 26import org.scalatest.matchers.must.Matchers 27import xiangshan.transforms.PrintModuleName 28 29import xiangshan.backend.fu._ 30 31import scala.util.Random 32 33 34class SRT4DividerWrapper extends Module { 35 val io = IO(new Bundle{ 36 val dividend = Input(UInt(64.W)) 37 val divisor = Input(UInt(64.W)) 38 val sign = Input(Bool()) 39 val isHi = Input(Bool()) 40 val isW = Input(Bool()) 41 val in_valid = Input(Bool()) 42 val out_ready = Input(Bool()) 43 val in_ready = Output(Bool()) 44 val out_valid = Output(Bool()) 45 val result = Output(UInt(64.W)) 46 }) 47 val divider = Module(new SRT16DividerDataModule(len = 64)) 48 divider.io.src(0) := io.dividend 49 divider.io.src(1) := io.divisor 50 divider.io.kill_r := false.B 51 divider.io.kill_w := false.B 52 divider.io.sign := io.sign 53 divider.io.isHi := io.isHi 54 divider.io.isW := io.isW 55 divider.io.out_ready := io.out_ready 56 divider.io.valid := io.in_valid 57 58 io.in_ready := divider.io.in_ready 59 io.out_valid := divider.io.out_valid 60 61 io.result := divider.io.out_data 62 63} 64 65class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers { 66 behavior of "srt16 divider" 67 it should "run" in { 68 val rand = new Random(0x14226) 69 val testNum = 1000 70 71 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation, 72 // LineCoverageAnnotation, 73 // ToggleCoverageAnnotation, 74 VerilatorFlags(Seq( 75 // "--output-split 20", "--output-split-cfuncs 20", 76 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")), 77 )){ m => 78 println("Test started!") 79 m.clock.step(20) 80 81 for (i <- 1 to testNum) { 82 m.clock.step(3) 83 m.io.in_ready.expect(true.B) 84 val divisor = rand.nextLong() 85 val dividend = rand.nextLong() 86 // val sign = rand.nextBoolean() 87 88 // val isSigned = if (sign) s"Signed division" else s"Unsigned division" 89 println(s"$i th iteration\n" + s"divisor is ${divisor.toHexString}, dividend is ${dividend.toHexString}") 90 m.io.in_valid.poke(true.B) 91 m.io.dividend.poke((s"b" + dividend.toBinaryString).asUInt(64.W)) 92 m.io.divisor.poke((s"b" + divisor.toBinaryString).asUInt(64.W)) 93 m.io.sign.poke(true.B) 94 val (quotient, remainder) = (dividend / divisor, dividend % divisor) 95 println(s"quotient is ${quotient.toHexString}, remainder is ${remainder.toHexString}") 96 var timeTaken = 0 97 while (m.io.out_valid.peek().litToBoolean != true) { 98 m.clock.step() 99 timeTaken += 1 100 if (timeTaken >= 62) assert(false, s"Timeout for single execution!!!") 101 } 102 103 m.io.in_valid.poke(false.B) 104 m.io.out_ready.poke(true.B) 105 m.io.isHi.poke(false.B) 106 m.clock.step() 107 108 m.io.result.expect((s"b" + quotient.toBinaryString).asUInt(64.W)) 109 m.io.isHi.poke(true.B) 110 m.clock.step() 111 112 m.io.result.expect((s"b" + remainder.toBinaryString).asUInt(64.W)) 113 } 114 } 115 } 116}