| #
e3da8bad |
| 22-Jul-2024 |
Tang Haojin <[email protected]> |
build: purge chisel 3 and add deprecation check (#3250)
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| #
5931ace3 |
| 26-Oct-2023 |
Tang Haojin <[email protected]> |
refactor directory hierarchy for two chisel versions (#2423)
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| #
da50abf9 |
| 25-Oct-2023 |
Tang Haojin <[email protected]> |
xstransform: support PrintControl and PrintModuleName for chisel6 (#2422)
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| #
51e45dbb |
| 11-Oct-2023 |
Tang Haojin <[email protected]> |
build: support chisel 3.6.0 and chisel 6.0.0-M3 (#2372)
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| #
51981c77 |
| 14-Feb-2023 |
bugGenerator <[email protected]> |
test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argp
test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
show more ...
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| #
9aca92b9 |
| 28-Sep-2021 |
Yinan Xu <[email protected]> |
misc: code clean up (#1073)
* rename Roq to Rob
* remove trailing whitespaces
* remove unused parameters
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| #
a58e3351 |
| 23-Sep-2021 |
Li Qianruo <[email protected]> |
Integer SRT16 Divider (#1019)
* New SRT4 divider that may improve timing
See "Digital reurrence dividers with reduced logical depth"
* SRT16 Int Divider that is working properly
* Fix bug r
Integer SRT16 Divider (#1019)
* New SRT4 divider that may improve timing
See "Digital reurrence dividers with reduced logical depth"
* SRT16 Int Divider that is working properly
* Fix bug related to div 1
* Timing improved version of SRT16 int divider
* Add copyright and made some minor changes
* Fix bugs related to div 0
* Fix another div 0 bug
* Fix another special case bug
show more ...
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