xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision f0856f80dcdd098a4ea44fe40706e7246d794cf3) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.backend.decode.isa.predecode.PreDecodeInst
7
8trait HasPdconst{ this: XSModule =>
9  val halfWidth = FetchWidth * 2
10  val groupAlign = log2Up(FetchWidth * 4)
11  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
12  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
13  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
14  def brInfo(instr: UInt) = {
15    val rd = instr(11,7)
16    val rs = instr(19,15)
17    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
18    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
19    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
20    List(brType, isCall, isRet)
21  }
22}
23
24object BrType {
25  def notBr   = "b00".U
26  def branch  = "b01".U
27  def jal     = "b10".U
28  def jalr    = "b11".U
29  def apply() = UInt(2.W)
30}
31
32object ExcType {  //TODO:add exctype
33  def notExc = "b000".U
34  def apply() = UInt(3.W)
35}
36
37class PDInfo extends XSBundle{  // 8 bit
38  val isRVC   = Bool()
39  val brType  = UInt(2.W)
40  val isCall  = Bool()
41  val isRet   = Bool()
42  val excType = UInt(3.W)
43}
44
45class PDPacket extends PDInfo{
46  val pc = UInt(VAddrBits.W)
47  val inst = UInt(32.W)
48  val mask = Bool()
49}
50
51class ICacheResp extends XSBundle {
52  val fetchPc = UInt(VAddrBits.W)
53  val data = UInt((FetchWidth * 32).W)
54  val mask = UInt((FetchWidth * 2).W)
55}
56
57class PreDecode extends XSModule with HasPdconst{
58  val io = IO(new Bundle() {
59    val in = Input(new ICacheResp)
60    val out = Output(Vec(halfWidth, new PDPacket))
61  })
62
63  val gpc = groupPC(io.in.fetchPc)
64  val data = io.in.data
65  val mask = io.in.mask
66
67  val insts = Wire(Vec(halfWidth, UInt(32.W)))
68  val instsMask = Wire(Vec(halfWidth, Bool()))
69  val instsRVC = Wire(Vec(halfWidth,Bool()))
70  val instsPC = Wire(Vec(halfWidth, UInt(VAddrBits.W)))
71
72
73  val prevHalf = Reg(UInt(16.W))
74  val prevValid = RegInit(false.B)
75  val prevGPC = RegInit(0.U(VAddrBits.W))
76  val seriesPC = RegInit(true.B)  //two cacheline's gpc is continuous
77  val nextHalf = Wire(UInt(16.W))
78
79  for (i <- 0 until halfWidth) {
80    val inst = Wire(UInt(32.W))
81    val valid = Wire(Bool())
82    val pc = gpc + (i << 1).U - Mux(prevValid && (i.U === 0.U), 2.U, 0.U)
83
84    if (i==0) {
85      inst := Mux(prevValid, Cat(data(15,0), prevHalf), data(31,0))
86      valid := true.B
87    } else if (i==1) {
88      inst := data(47,16)
89      valid := prevValid || !(instsMask(0) && !isRVC(insts(0)))
90    } else if (i==halfWidth-1) {
91      inst := Cat(0.U(16.W), data(i*16+15, i*16))
92      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
93    } else {
94      inst := data(i*16+31, i*16)
95      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
96    }
97
98    insts(i) := inst
99    instsRVC(i) := isRVC(inst)
100    instsMask(i) := mask(i) && valid
101    instsPC(i) := pc
102
103    val brType::isCall::isRet::Nil = brInfo(inst)
104    io.out(i).isRVC := instsRVC(i)
105    io.out(i).brType := brType
106    io.out(i).isCall := isCall
107    io.out(i).isRet := isRet
108    io.out(i).excType := ExcType.notExc
109    io.out(i).inst := insts(i)
110    io.out(i).mask := instsMask(i)
111    io.out(i).pc := instsPC(i)
112  }
113
114  //update
115  nextHalf := data(halfWidth*16-1, (halfWidth-1)*16)
116  prevHalf := nextHalf
117  seriesPC := 1.U === (gpc - prevGPC)(VAddrBits-1, groupAlign)
118  prevGPC := gpc
119  prevValid := !(instsMask(halfWidth-2) && !isRVC(insts(halfWidth-2))) && !isRVC(insts(halfWidth-1)) && seriesPC
120
121//  for (i <- 0 until halfWidth) {
122//    XSDebug(true.B,
123//      p"instr ${Binary(io.out(i).inst)}, " +
124//      p"mask ${Binary(io.out(i).mask)}, " +
125//      //p"pc ${Binary(io.out(i).pc)}, " +
126//      p"isRVC ${Binary(io.out(i).isRVC)}, " +
127//      p"brType ${Binary(io.out(i).brType)}, " +
128//      p"isRet ${Binary(io.out(i).isRet)}, " +
129//      p"isCall ${Binary(io.out(i).isCall)}\n"
130//    )
131//  }
132//
133//  for (i <- 0 until halfWidth) {
134//    XSDebug(true.B,
135//      p"prevhalf ${Binary(prevHalf)}, " +
136//      p"prevvalid ${Binary(prevValid)}, " +
137//      p"seriesPC ${Binary(seriesPC)}\n"
138//    )
139//  }
140}
141