xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision dfddd710a529ee7a9c492b0952587b8a3330cc74) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils.XSDebug
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8
9trait HasPdconst{ this: XSModule =>
10  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
11  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
12  def brInfo(instr: UInt) = {
13    val rd = instr(11,7)
14    val rs = instr(19,15)
15    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
16    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
17    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
18    List(brType, isCall, isRet)
19  }
20}
21
22object BrType {
23  def notBr   = "b00".U
24  def branch  = "b01".U
25  def jal     = "b10".U
26  def jalr    = "b11".U
27  def apply() = UInt(2.W)
28}
29
30object ExcType {  //TODO:add exctype
31  def notExc = "b000".U
32  def apply() = UInt(3.W)
33}
34
35class PreDecodeInfo extends XSBundle {  // 8 bit
36  val isRVC   = Bool()
37  val brType  = UInt(2.W)
38  val isCall  = Bool()
39  val isRet   = Bool()
40  val excType = UInt(3.W)
41  def isBr = brType === BrType.branch
42  def isJal = brType === BrType.jal
43  def isJalr = brType === BrType.jalr
44}
45
46class PreDecodeResp extends XSBundle {
47  val instrs = Vec(PredictWidth, UInt(32.W))
48  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
49  val mask = UInt(PredictWidth.W)
50  val pd = Vec(PredictWidth, (new PreDecodeInfo))
51}
52
53class PreDecode extends XSModule with HasPdconst{
54  val io = IO(new Bundle() {
55    val in = Input(new FakeIcacheResp)
56    val prev = Flipped(ValidIO(UInt(16.W)))
57    val out = Output(new PreDecodeResp)
58  })
59
60  val data = io.in.data
61  val mask = io.in.mask
62
63  val insts = Wire(Vec(PredictWidth, UInt(32.W)))
64  val instsMask = Wire(Vec(PredictWidth, Bool()))
65  val instsRVC = Wire(Vec(PredictWidth,Bool()))
66  val instsPC = Wire(Vec(PredictWidth, UInt(VAddrBits.W)))
67  val nextHalf = Wire(UInt(16.W))
68
69  val lastHalfInstrIdx = PopCount(mask) - 1.U
70
71  for (i <- 0 until PredictWidth) {
72    val inst = Wire(UInt(32.W))
73    val valid = Wire(Bool())
74    val pc = io.in.pc + (i << 1).U - Mux(io.prev.valid && (i.U === 0.U), 2.U, 0.U)
75
76    if (i==0) {
77      inst := Mux(io.prev.valid, Cat(data(15,0), io.prev.bits), data(31,0))
78      valid := true.B
79    } else if (i==1) {
80      inst := data(47,16)
81      valid := io.prev.valid || !(instsMask(0) && !isRVC(insts(0)))
82    } else if (i==PredictWidth-1) {
83      inst := Cat(0.U(16.W), data(i*16+15, i*16))
84      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
85    } else {
86      inst := data(i*16+31, i*16)
87      valid := !(instsMask(i-1) && !isRVC(insts(i-1))) && Mux(i.U === lastHalfInstrIdx, isRVC(inst), true.B)
88    }
89
90    insts(i) := inst
91    instsRVC(i) := isRVC(inst)
92    instsMask(i) := mask(i) && valid
93    instsPC(i) := pc
94
95    val brType::isCall::isRet::Nil = brInfo(inst)
96    io.out.pd(i).isRVC := instsRVC(i)
97    io.out.pd(i).brType := brType
98    io.out.pd(i).isCall := isCall
99    io.out.pd(i).isRet := isRet
100    io.out.pd(i).excType := ExcType.notExc
101    io.out.instrs(i) := insts(i)
102    io.out.pc(i) := instsPC(i)
103
104  }
105  io.out.mask := instsMask.asUInt
106
107  for (i <- 0 until PredictWidth) {
108    XSDebug(true.B,
109      p"instr ${Hexadecimal(io.out.instrs(i))}, " +
110      p"mask ${Binary(instsMask(i))}, " +
111      p"pc ${Hexadecimal(io.out.pc(i))}, " +
112      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
113      p"brType ${Binary(io.out.pd(i).brType)}, " +
114      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
115      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
116    )
117  }
118}
119