1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import utility._ 25import xiangshan._ 26import xiangshan.frontend.icache._ 27import xiangshan.backend.decode.isa.predecode.PreDecodeInst 28import java.lang.reflect.Parameter 29import xiangshan.backend.fu.util.SdtrigExt 30 31trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 32 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 33 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 34 def brInfo(instr: UInt) = { 35 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 36 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 37 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 38 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 39 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 40 List(brType, isCall, isRet) 41 } 42 def jal_offset(inst: UInt, rvc: Bool): UInt = { 43 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 44 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 45 val max_width = rvi_offset.getWidth 46 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 47 } 48 def br_offset(inst: UInt, rvc: Bool): UInt = { 49 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 50 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 51 val max_width = rvi_offset.getWidth 52 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 53 } 54 55 def NOP = "h4501".U(16.W) 56} 57 58object BrType { 59 def notCFI = "b00".U 60 def branch = "b01".U 61 def jal = "b10".U 62 def jalr = "b11".U 63 def apply() = UInt(2.W) 64} 65 66object ExcType { //TODO:add exctype 67 def notExc = "b000".U 68 def apply() = UInt(3.W) 69} 70 71class PreDecodeInfo extends Bundle { // 8 bit 72 val valid = Bool() 73 val isRVC = Bool() 74 val brType = UInt(2.W) 75 val isCall = Bool() 76 val isRet = Bool() 77 //val excType = UInt(3.W) 78 def isBr = brType === BrType.branch 79 def isJal = brType === BrType.jal 80 def isJalr = brType === BrType.jalr 81 def notCFI = brType === BrType.notCFI 82} 83 84class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 85 val pd = Vec(PredictWidth, new PreDecodeInfo) 86 val hasHalfValid = Vec(PredictWidth, Bool()) 87 //val expInstr = Vec(PredictWidth, UInt(32.W)) 88 val instr = Vec(PredictWidth, UInt(32.W)) 89 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 90// val hasLastHalf = Bool() 91 val triggered = Vec(PredictWidth, new TriggerCf) 92} 93 94class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 95 val io = IO(new Bundle() { 96 val in = Input(ValidIO(new IfuToPreDecode)) 97 val out = Output(new PreDecodeResp) 98 }) 99 100 val data = io.in.bits.data 101// val lastHalfMatch = io.in.lastHalfMatch 102 val validStart, validEnd = Wire(Vec(PredictWidth, Bool())) 103 val h_validStart, h_validEnd = Wire(Vec(PredictWidth, Bool())) 104 105 val validStart_half, validEnd_half = Wire(Vec(PredictWidth, Bool())) 106 val h_validStart_half, h_validEnd_half = Wire(Vec(PredictWidth, Bool())) 107 108 val validStart_halfPlus1, validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 109 val h_validStart_halfPlus1, h_validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 110 111 val validStart_diff, validEnd_diff = Wire(Vec(PredictWidth, Bool())) 112 val h_validStart_diff, h_validEnd_diff = Wire(Vec(PredictWidth, Bool())) 113 114 val currentIsRVC = Wire(Vec(PredictWidth, Bool())) 115 116 validStart_half.map(_ := false.B) 117 validEnd_half.map(_ := false.B) 118 h_validStart_half.map(_ := false.B) 119 h_validEnd_half.map(_ := false.B) 120 121 validStart_halfPlus1.map(_ := false.B) 122 validEnd_halfPlus1.map(_ := false.B) 123 h_validStart_halfPlus1.map(_ := false.B) 124 h_validEnd_halfPlus1.map(_ := false.B) 125 126 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 127 else VecInit((0 until PredictWidth).map(i => data(i))) 128 129 for (i <- 0 until PredictWidth) { 130 val inst = WireInit(rawInsts(i)) 131 //val expander = Module(new RVCExpander) 132 currentIsRVC(i) := isRVC(inst) 133 val currentPC = io.in.bits.pc(i) 134 //expander.io.in := inst 135 136 val brType::isCall::isRet::Nil = brInfo(inst) 137 val jalOffset = jal_offset(inst, currentIsRVC(i)) 138 val brOffset = br_offset(inst, currentIsRVC(i)) 139 140 io.out.hasHalfValid(i) := h_validStart(i) 141 142 io.out.triggered(i) := DontCare//VecInit(Seq.fill(10)(false.B)) 143 144 145 io.out.pd(i).valid := validStart(i) 146 io.out.pd(i).isRVC := currentIsRVC(i) 147 148 // for diff purpose only 149 io.out.pd(i).brType := brType 150 io.out.pd(i).isCall := isCall 151 io.out.pd(i).isRet := isRet 152 153 //io.out.expInstr(i) := expander.io.out.bits 154 io.out.instr(i) :=inst 155 io.out.jumpOffset(i) := Mux(io.out.pd(i).isBr, brOffset, jalOffset) 156 } 157 158 // the first half is always reliable 159 for (i <- 0 until PredictWidth / 2) { 160 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd(i-1) || !HasCExtension.B } 161 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 162 validEnd(i) := validStart(i) && currentIsRVC(i) || !validStart(i) || !HasCExtension.B 163 164 //prepared for last half match 165 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd(i-1) || !HasCExtension.B } 166 h_validStart(i) := (h_lastIsValidEnd || !HasCExtension.B) 167 h_validEnd(i) := h_validStart(i) && currentIsRVC(i) || !h_validStart(i) || !HasCExtension.B 168 } 169 170 for (i <- 0 until PredictWidth) { 171 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd_diff(i-1) || !HasCExtension.B } 172 validStart_diff(i) := (lastIsValidEnd || !HasCExtension.B) 173 validEnd_diff(i) := validStart_diff(i) && currentIsRVC(i) || !validStart_diff(i) || !HasCExtension.B 174 175 //prepared for last half match 176 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd_diff(i-1) || !HasCExtension.B } 177 h_validStart_diff(i) := (h_lastIsValidEnd || !HasCExtension.B) 178 h_validEnd_diff(i) := h_validStart_diff(i) && currentIsRVC(i) || !h_validStart_diff(i) || !HasCExtension.B 179 } 180 181 // assume PredictWidth / 2 is a valid start 182 for (i <- PredictWidth / 2 until PredictWidth) { 183 val lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { validEnd_half(i-1) || !HasCExtension.B } 184 validStart_half(i) := (lastIsValidEnd || !HasCExtension.B) 185 validEnd_half(i) := validStart_half(i) && currentIsRVC(i) || !validStart_half(i) || !HasCExtension.B 186 187 //prepared for last half match 188 val h_lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { h_validEnd_half(i-1) || !HasCExtension.B } 189 h_validStart_half(i) := (h_lastIsValidEnd || !HasCExtension.B) 190 h_validEnd_half(i) := h_validStart_half(i) && currentIsRVC(i) || !h_validStart_half(i) || !HasCExtension.B 191 } 192 193 // assume PredictWidth / 2 + 1 is a valid start (and PredictWidth / 2 is last half of RVI) 194 for (i <- PredictWidth / 2 + 1 until PredictWidth) { 195 val lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { validEnd_halfPlus1(i-1) || !HasCExtension.B } 196 validStart_halfPlus1(i) := (lastIsValidEnd || !HasCExtension.B) 197 validEnd_halfPlus1(i) := validStart_halfPlus1(i) && currentIsRVC(i) || !validStart_halfPlus1(i) || !HasCExtension.B 198 199 //prepared for last half match 200 val h_lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { h_validEnd_halfPlus1(i-1) || !HasCExtension.B } 201 h_validStart_halfPlus1(i) := (h_lastIsValidEnd || !HasCExtension.B) 202 h_validEnd_halfPlus1(i) := h_validStart_halfPlus1(i) && currentIsRVC(i) || !h_validStart_halfPlus1(i) || !HasCExtension.B 203 } 204 validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 205 validEnd_halfPlus1(PredictWidth / 2) := true.B 206 207 // assume h_PredictWidth / 2 is an end 208 h_validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 209 h_validEnd_halfPlus1(PredictWidth / 2) := true.B 210 211 // if PredictWidth / 2 - 1 is a valid end, PredictWidth / 2 is a valid start 212 for (i <- PredictWidth / 2 until PredictWidth) { 213 validStart(i) := Mux(validEnd(PredictWidth / 2 - 1), validStart_half(i), validStart_halfPlus1(i)) 214 validEnd(i) := Mux(validEnd(PredictWidth / 2 - 1), validEnd_half(i), validEnd_halfPlus1(i)) 215 h_validStart(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validStart_half(i), h_validStart_halfPlus1(i)) 216 h_validEnd(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validEnd_half(i), h_validEnd_halfPlus1(i)) 217 } 218 219 val validStartMismatch = Wire(Bool()) 220 val validEndMismatch = Wire(Bool()) 221 val validH_ValidStartMismatch = Wire(Bool()) 222 val validH_ValidEndMismatch = Wire(Bool()) 223 224 validStartMismatch := validStart.zip(validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 225 validEndMismatch := validEnd.zip(validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 226 validH_ValidStartMismatch := h_validStart.zip(h_validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 227 validH_ValidEndMismatch := h_validEnd.zip(h_validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 228 229 XSError(io.in.valid && validStartMismatch, p"validStart mismatch\n") 230 XSError(io.in.valid && validEndMismatch, p"validEnd mismatch\n") 231 XSError(io.in.valid && validH_ValidStartMismatch, p"h_validStart mismatch\n") 232 XSError(io.in.valid && validH_ValidEndMismatch, p"h_validEnd mismatch\n") 233 234// io.out.hasLastHalf := !io.out.pd(PredictWidth - 1).isRVC && io.out.pd(PredictWidth - 1).valid 235 236 for (i <- 0 until PredictWidth) { 237 XSDebug(true.B, 238 p"instr ${Hexadecimal(io.out.instr(i))}, " + 239 p"validStart ${Binary(validStart(i))}, " + 240 p"validEnd ${Binary(validEnd(i))}, " + 241 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 242 p"brType ${Binary(io.out.pd(i).brType)}, " + 243 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 244 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 245 ) 246 } 247} 248 249class IfuToF3PreDecode(implicit p: Parameters) extends XSBundle with HasPdConst { 250 val instr = Vec(PredictWidth, UInt(32.W)) 251} 252 253class F3PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 254 val pd = Vec(PredictWidth, new PreDecodeInfo) 255} 256class F3Predecoder(implicit p: Parameters) extends XSModule with HasPdConst { 257 val io = IO(new Bundle() { 258 val in = Input(new IfuToF3PreDecode) 259 val out = Output(new F3PreDecodeResp) 260 }) 261 io.out.pd.zipWithIndex.map{ case (pd,i) => 262 pd.valid := DontCare 263 pd.isRVC := DontCare 264 pd.brType := brInfo(io.in.instr(i))(0) 265 pd.isCall := brInfo(io.in.instr(i))(1) 266 pd.isRet := brInfo(io.in.instr(i))(2) 267 } 268 269} 270 271class RVCExpander(implicit p: Parameters) extends XSModule { 272 val io = IO(new Bundle { 273 val in = Input(UInt(32.W)) 274 val out = Output(new ExpandedInstruction) 275 }) 276 277 if (HasCExtension) { 278 io.out := new RVCDecoder(io.in, XLEN, fLen, useAddiForMv = true).decode 279 } else { 280 io.out := new RVCDecoder(io.in, XLEN, fLen, useAddiForMv = true).passthrough 281 } 282} 283 284/* --------------------------------------------------------------------- 285 * Predict result check 286 * 287 * --------------------------------------------------------------------- 288 */ 289 290object FaultType { 291 def noFault = "b000".U 292 def jalFault = "b001".U //not CFI taken or invalid instruction taken 293 def retFault = "b010".U //not CFI taken or invalid instruction taken 294 def targetFault = "b011".U 295 def notCFIFault = "b100".U //not CFI taken or invalid instruction taken 296 def invalidTaken = "b101".U 297 def apply() = UInt(3.W) 298} 299 300class CheckInfo extends Bundle { // 8 bit 301 val value = UInt(3.W) 302 def isjalFault = value === FaultType.jalFault 303 def isRetFault = value === FaultType.retFault 304 def istargetFault = value === FaultType.targetFault 305 def invalidTakenFault = value === FaultType.invalidTaken 306 def notCFIFault = value === FaultType.notCFIFault 307} 308 309class PredCheckerResp(implicit p: Parameters) extends XSBundle with HasPdConst { 310 //to Ibuffer write port (stage 1) 311 val stage1Out = new Bundle{ 312 val fixedRange = Vec(PredictWidth, Bool()) 313 val fixedTaken = Vec(PredictWidth, Bool()) 314 } 315 //to Ftq write back port (stage 2) 316 val stage2Out = new Bundle{ 317 val fixedTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 318 val jalTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 319 val fixedMissPred = Vec(PredictWidth, Bool()) 320 val faultType = Vec(PredictWidth, new CheckInfo) 321 } 322} 323 324 325class PredChecker(implicit p: Parameters) extends XSModule with HasPdConst { 326 val io = IO( new Bundle{ 327 val in = Input(new IfuToPredChecker) 328 val out = Output(new PredCheckerResp) 329 }) 330 331 val (takenIdx, predTaken) = (io.in.ftqOffset.bits, io.in.ftqOffset.valid) 332 val predTarget = (io.in.target) 333 val (instrRange, instrValid) = (io.in.instrRange, io.in.instrValid) 334 val (pds, pc, jumpOffset) = (io.in.pds, io.in.pc, io.in.jumpOffset) 335 336 val jalFaultVec, retFaultVec, targetFault, notCFITaken, invalidTaken = Wire(Vec(PredictWidth, Bool())) 337 338 /** remask fault may appear together with other faults, but other faults are exclusive 339 * so other f ault mast use fixed mask to keep only one fault would be found and redirect to Ftq 340 * we first detecct remask fault and then use fixedRange to do second check 341 **/ 342 343 //Stage 1: detect remask fault 344 /** first check: remask Fault */ 345 jalFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isJal && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 346 retFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isRet && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 347 val remaskFault = VecInit((0 until PredictWidth).map(i => jalFaultVec(i) || retFaultVec(i))) 348 val remaskIdx = ParallelPriorityEncoder(remaskFault.asUInt) 349 val needRemask = ParallelOR(remaskFault) 350 val fixedRange = instrRange.asUInt & (Fill(PredictWidth, !needRemask) | Fill(PredictWidth, 1.U(1.W)) >> ~remaskIdx) 351 352 io.out.stage1Out.fixedRange := fixedRange.asTypeOf((Vec(PredictWidth, Bool()))) 353 354 io.out.stage1Out.fixedTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => instrValid (i) && fixedRange(i) && (pd.isRet || pd.isJal || takenIdx === i.U && predTaken && !pd.notCFI) }) 355 356 /** second check: faulse prediction fault and target fault */ 357 notCFITaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && instrValid(i) && i.U === takenIdx && pd.notCFI && predTaken }) 358 invalidTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && !instrValid(i) && i.U === takenIdx && predTaken }) 359 360 val jumpTargets = VecInit(pds.zipWithIndex.map{case(pd,i) => (pc(i) + jumpOffset(i)).asTypeOf(UInt(VAddrBits.W))}) 361 val seqTargets = VecInit((0 until PredictWidth).map(i => pc(i) + Mux(pds(i).isRVC || !instrValid(i), 2.U, 4.U ) )) 362 363 //Stage 2: detect target fault 364 /** target calculation: in the next stage */ 365 val fixedRangeNext = RegEnable(fixedRange, io.in.fire_in) 366 val instrValidNext = RegEnable(instrValid, io.in.fire_in) 367 val takenIdxNext = RegEnable(takenIdx, io.in.fire_in) 368 val predTakenNext = RegEnable(predTaken, io.in.fire_in) 369 val predTargetNext = RegEnable(predTarget, io.in.fire_in) 370 val jumpTargetsNext = RegEnable(jumpTargets, io.in.fire_in) 371 val seqTargetsNext = RegEnable(seqTargets, io.in.fire_in) 372 val pdsNext = RegEnable(pds, io.in.fire_in) 373 val jalFaultVecNext = RegEnable(jalFaultVec, io.in.fire_in) 374 val retFaultVecNext = RegEnable(retFaultVec, io.in.fire_in) 375 val notCFITakenNext = RegEnable(notCFITaken, io.in.fire_in) 376 val invalidTakenNext = RegEnable(invalidTaken, io.in.fire_in) 377 378 targetFault := VecInit(pdsNext.zipWithIndex.map{case(pd,i) => fixedRangeNext(i) && instrValidNext(i) && (pd.isJal || pd.isBr) && takenIdxNext === i.U && predTakenNext && (predTargetNext =/= jumpTargetsNext(i))}) 379 380 381 io.out.stage2Out.faultType.zipWithIndex.foreach{case(faultType, i) => faultType.value := Mux(jalFaultVecNext(i) , FaultType.jalFault , 382 Mux(retFaultVecNext(i), FaultType.retFault , 383 Mux(targetFault(i), FaultType.targetFault , 384 Mux(notCFITakenNext(i) , FaultType.notCFIFault, 385 Mux(invalidTakenNext(i), FaultType.invalidTaken, FaultType.noFault)))))} 386 387 io.out.stage2Out.fixedMissPred.zipWithIndex.foreach{case(missPred, i ) => missPred := jalFaultVecNext(i) || retFaultVecNext(i) || notCFITakenNext(i) || invalidTakenNext(i) || targetFault(i)} 388 io.out.stage2Out.fixedTarget.zipWithIndex.foreach{case(target, i) => target := Mux(jalFaultVecNext(i) || targetFault(i), jumpTargetsNext(i), seqTargetsNext(i) )} 389 io.out.stage2Out.jalTarget.zipWithIndex.foreach{case(target, i) => target := jumpTargetsNext(i) } 390 391} 392 393class FrontendTrigger(implicit p: Parameters) extends XSModule with SdtrigExt { 394 val io = IO(new Bundle(){ 395 val frontendTrigger = Input(new FrontendTdataDistributeIO) 396 val triggered = Output(Vec(PredictWidth, new TriggerCf)) 397 398 val pds = Input(Vec(PredictWidth, new PreDecodeInfo)) 399 val pc = Input(Vec(PredictWidth, UInt(VAddrBits.W))) 400 val data = if(HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) 401 else Input(Vec(PredictWidth, UInt(32.W))) 402 }) 403 404 val data = io.data 405 406 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 407 else VecInit((0 until PredictWidth).map(i => data(i))) 408 409 val tdata = RegInit(VecInit(Seq.fill(TriggerNum)(0.U.asTypeOf(new MatchTriggerIO)))) 410 when(io.frontendTrigger.tUpdate.valid) { 411 tdata(io.frontendTrigger.tUpdate.bits.addr) := io.frontendTrigger.tUpdate.bits.tdata 412 } 413 val triggerEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) // From CSR, controlled by priv mode, etc. 414 triggerEnableVec := io.frontendTrigger.tEnableVec 415 XSDebug(triggerEnableVec.asUInt.orR, "Debug Mode: At least one frontend trigger is enabled\n") 416 417 val triggerTimingVec = VecInit(tdata.map(_.timing)) 418 val triggerChainVec = VecInit(tdata.map(_.chain)) 419 420 for (i <- 0 until TriggerNum) { PrintTriggerInfo(triggerEnableVec(i), tdata(i)) } 421 422 //val triggerHitVec = Wire(Vec(PredictWidth, Vec(TriggerNum, Bool()))) 423 val triggerHitVec = (0 until TriggerNum).map(j => 424 TriggerCmpConsecutive(io.pc, tdata(j).tdata2, tdata(j).matchType, triggerEnableVec(j)).map( 425 hit => hit && !tdata(j).select) 426 ).transpose 427 428 for (i <- 0 until PredictWidth) { 429 val triggerCanFireVec = Wire(Vec(TriggerNum, Bool())) 430 TriggerCheckCanFire(TriggerNum, triggerCanFireVec, VecInit(triggerHitVec(i)), triggerTimingVec, triggerChainVec) 431 // only hit, no matter fire or not 432 io.triggered(i).frontendHit := triggerHitVec(i) 433 // can fire, exception will be handled at rob enq 434 io.triggered(i).frontendCanFire := triggerCanFireVec 435 XSDebug(io.triggered(i).getFrontendCanFire, p"Debug Mode: Predecode Inst No. ${i} has trigger fire vec ${io.triggered(i).frontendCanFire}\n") 436 } 437 io.triggered.foreach(_.backendCanFire := VecInit(Seq.fill(TriggerNum)(false.B))) 438 io.triggered.foreach(_.backendHit := VecInit(Seq.fill(TriggerNum)(false.B))) 439} 440