xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision 667ccea8598d5889ea58e79ab790a1b131db6533) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils.XSDebug
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8
9trait HasPdconst{ this: XSModule =>
10  val halfWidth = FetchWidth * 2
11  val groupAlign = log2Up(FetchWidth * 4)
12  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
13  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
14  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
15  def brInfo(instr: UInt) = {
16    val rd = instr(11,7)
17    val rs = instr(19,15)
18    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
19    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
20    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
21    List(brType, isCall, isRet)
22  }
23}
24
25object BrType {
26  def notBr   = "b00".U
27  def branch  = "b01".U
28  def jal     = "b10".U
29  def jalr    = "b11".U
30  def apply() = UInt(2.W)
31}
32
33object ExcType {  //TODO:add exctype
34  def notExc = "b000".U
35  def apply() = UInt(3.W)
36}
37
38class PDInfo extends XSBundle{  // 8 bit
39  val isRVC   = Bool()
40  val brType  = UInt(2.W)
41  val isCall  = Bool()
42  val isRet   = Bool()
43  val excType = UInt(3.W)
44}
45
46class PDPacket extends PDInfo{
47  val pc = UInt(VAddrBits.W)
48  val inst = UInt(32.W)
49  val mask = Bool()
50}
51
52class ICacheResp extends XSBundle {
53  val fetchPc = UInt(VAddrBits.W)
54  val data = UInt((FetchWidth * 32).W)
55  val mask = UInt((FetchWidth * 2).W)
56}
57
58class PreDecode extends XSModule with HasPdconst{
59  val io = IO(new Bundle() {
60    val in = Input(new ICacheResp)
61    val out = Output(Vec(halfWidth, new PDPacket))
62  })
63
64  val gpc = groupPC(io.in.fetchPc)
65  val data = io.in.data
66  val mask = io.in.mask
67
68  val insts = Wire(Vec(halfWidth, UInt(32.W)))
69  val instsMask = Wire(Vec(halfWidth, Bool()))
70  val instsRVC = Wire(Vec(halfWidth,Bool()))
71  val instsPC = Wire(Vec(halfWidth, UInt(VAddrBits.W)))
72
73
74  val prevHalf = Reg(UInt(16.W))
75  val prevValid = RegInit(false.B)
76  val prevGPC = RegInit(0.U(VAddrBits.W))
77  val seriesPC = RegInit(true.B)  //two cacheline's gpc is continuous
78  val nextHalf = Wire(UInt(16.W))
79
80  for (i <- 0 until halfWidth) {
81    val inst = Wire(UInt(32.W))
82    val valid = Wire(Bool())
83    val pc = gpc + (i << 1).U - Mux(prevValid && (i.U === 0.U), 2.U, 0.U)
84
85    if (i==0) {
86      inst := Mux(prevValid, Cat(data(15,0), prevHalf), data(31,0))
87      valid := true.B
88    } else if (i==1) {
89      inst := data(47,16)
90      valid := prevValid || !(instsMask(0) && !isRVC(insts(0)))
91    } else if (i==halfWidth-1) {
92      inst := Cat(0.U(16.W), data(i*16+15, i*16))
93      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
94    } else {
95      inst := data(i*16+31, i*16)
96      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
97    }
98
99    insts(i) := inst
100    instsRVC(i) := isRVC(inst)
101    instsMask(i) := mask(i) && valid
102    instsPC(i) := pc
103
104    val brType::isCall::isRet::Nil = brInfo(inst)
105    io.out(i).isRVC := instsRVC(i)
106    io.out(i).brType := brType
107    io.out(i).isCall := isCall
108    io.out(i).isRet := isRet
109    io.out(i).excType := ExcType.notExc
110    io.out(i).inst := insts(i)
111    io.out(i).mask := instsMask(i)
112    io.out(i).pc := instsPC(i)
113  }
114
115  //update
116  nextHalf := data(halfWidth*16-1, (halfWidth-1)*16)
117  prevHalf := nextHalf
118  seriesPC := 1.U === (gpc - prevGPC)(VAddrBits-1, groupAlign)
119  prevGPC := gpc
120  prevValid := !(instsMask(halfWidth-2) && !isRVC(insts(halfWidth-2))) && !isRVC(insts(halfWidth-1)) && seriesPC
121
122  for (i <- 0 until halfWidth) {
123    XSDebug(true.B,
124      p"instr ${Binary(io.out(i).inst)}, " +
125      p"mask ${Binary(io.out(i).mask)}, " +
126      //p"pc ${Binary(io.out(i).pc)}, " +
127      p"isRVC ${Binary(io.out(i).isRVC)}, " +
128      p"brType ${Binary(io.out(i).brType)}, " +
129      p"isRet ${Binary(io.out(i).isRet)}, " +
130      p"isCall ${Binary(io.out(i).isCall)}\n"
131    )
132  }
133
134  for (i <- 0 until halfWidth) {
135    XSDebug(true.B,
136      p"prevhalf ${Binary(prevHalf)}, " +
137      p"prevvalid ${Binary(prevValid)}, " +
138      p"seriesPC ${Binary(seriesPC)}\n"
139    )
140  }
141}
142