xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision 4c18e8036de7d8e3e33ac0ccd34d1f9f84fdb982) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils.XSDebug
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8
9trait HasPdconst{ this: XSModule =>
10  val halfWidth = FetchWidth * 2
11  val groupAlign = log2Up(FetchWidth * 4)
12  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
13  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
14  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
15  def brInfo(instr: UInt) = {
16    val rd = instr(11,7)
17    val rs = instr(19,15)
18    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
19    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
20    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
21    List(brType, isCall, isRet)
22  }
23}
24
25object BrType {
26  def notBr   = "b00".U
27  def branch  = "b01".U
28  def jal     = "b10".U
29  def jalr    = "b11".U
30  def apply() = UInt(2.W)
31}
32
33object ExcType {  //TODO:add exctype
34  def notExc = "b000".U
35  def apply() = UInt(3.W)
36}
37
38class PDInfo extends XSBundle{  // 8 bit
39  val isRVC   = Bool()
40  val brType  = UInt(2.W)
41  val isCall  = Bool()
42  val isRet   = Bool()
43  val excType = UInt(3.W)
44}
45
46class PDPacket extends PDInfo{
47  val pc = UInt(VAddrBits.W)
48  val inst = UInt(32.W)
49  val mask = Bool()
50}
51
52class ICacheResp extends XSBundle {
53  val fetchPc = UInt(VAddrBits.W)
54  val data = UInt((FetchWidth * 32).W)
55  val mask = UInt((FetchWidth * 2).W)
56}
57
58class PreDecode extends XSModule with HasPdconst{
59  val io = IO(new Bundle() {
60    val in = Input(new ICacheResp)
61    val prevHalf = Input(UInt(16.W))
62    val prevValid = Input(false.B)
63
64    val out = Output(Vec(halfWidth, new PDPacket))
65  })
66
67  val gpc = groupPC(io.in.fetchPc)
68  val data = io.in.data
69  val mask = io.in.mask
70
71  val insts = Wire(Vec(halfWidth, UInt(32.W)))
72  val instsMask = Wire(Vec(halfWidth, Bool()))
73  val instsRVC = Wire(Vec(halfWidth,Bool()))
74  val instsPC = Wire(Vec(halfWidth, UInt(VAddrBits.W)))
75  val nextHalf = Wire(UInt(16.W))
76
77  for (i <- 0 until halfWidth) {
78    val inst = Wire(UInt(32.W))
79    val valid = Wire(Bool())
80    val pc = gpc + (i << 1).U - Mux(io.prevValid && (i.U === 0.U), 2.U, 0.U)
81
82    if (i==0) {
83      inst := Mux(io.prevValid, Cat(data(15,0), io.prevHalf), data(31,0))
84      valid := true.B
85    } else if (i==1) {
86      inst := data(47,16)
87      valid := io.prevValid || !(instsMask(0) && !isRVC(insts(0)))
88    } else if (i==halfWidth-1) {
89      inst := Cat(0.U(16.W), data(i*16+15, i*16))
90      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
91    } else {
92      inst := data(i*16+31, i*16)
93      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
94    }
95
96    insts(i) := inst
97    instsRVC(i) := isRVC(inst)
98    instsMask(i) := mask(i) && valid
99    instsPC(i) := pc
100
101    val brType::isCall::isRet::Nil = brInfo(inst)
102    io.out(i).isRVC := instsRVC(i)
103    io.out(i).brType := brType
104    io.out(i).isCall := isCall
105    io.out(i).isRet := isRet
106    io.out(i).excType := ExcType.notExc
107    io.out(i).inst := insts(i)
108    io.out(i).mask := instsMask(i)
109    io.out(i).pc := instsPC(i)
110  }
111
112
113  for (i <- 0 until halfWidth) {
114    XSDebug(true.B,
115      p"instr ${Binary(io.out(i).inst)}, " +
116      p"mask ${Binary(io.out(i).mask)}, " +
117      //p"pc ${Binary(io.out(i).pc)}, " +
118      p"isRVC ${Binary(io.out(i).isRVC)}, " +
119      p"brType ${Binary(io.out(i).brType)}, " +
120      p"isRet ${Binary(io.out(i).isRet)}, " +
121      p"isCall ${Binary(io.out(i).isCall)}\n"
122    )
123  }
124}
125