xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision 42696a74b557c216a8a1ec416550e34c8f43c6af) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils.XSDebug
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8
9trait HasPdconst{ this: XSModule =>
10  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
11  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
12  def brInfo(instr: UInt) = {
13    val rd = instr(11,7)
14    val rs = instr(19,15)
15    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
16    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
17    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
18    List(brType, isCall, isRet)
19  }
20}
21
22object BrType {
23  def notBr   = "b00".U
24  def branch  = "b01".U
25  def jal     = "b10".U
26  def jalr    = "b11".U
27  def apply() = UInt(2.W)
28}
29
30object ExcType {  //TODO:add exctype
31  def notExc = "b000".U
32  def apply() = UInt(3.W)
33}
34
35class PreDecodeInfo extends XSBundle {  // 8 bit
36  val isRVC   = Bool()
37  val brType  = UInt(2.W)
38  val isCall  = Bool()
39  val isRet   = Bool()
40  val excType = UInt(3.W)
41}
42
43class PreDecodeResp extends XSBundle {
44  val instrs = Vec(PredictWidth, UInt(32.W))
45  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
46  val mask = UInt(PredictWidth.W)
47  val pd = Vec(PredictWidth, (new PreDecodeInfo))
48}
49
50class PreDecode extends XSModule with HasPdconst{
51  val io = IO(new Bundle() {
52    val in = Input(new FakeIcacheResp)
53    val prev = Flipped(ValidIO(UInt(16.W)))
54    val out = Output(new PreDecodeResp)
55  })
56
57  val data = io.in.data
58  val mask = io.in.mask
59
60  val insts = Wire(Vec(PredictWidth, UInt(32.W)))
61  val instsMask = Wire(Vec(PredictWidth, Bool()))
62  val instsRVC = Wire(Vec(PredictWidth,Bool()))
63  val instsPC = Wire(Vec(PredictWidth, UInt(VAddrBits.W)))
64  val nextHalf = Wire(UInt(16.W))
65
66  for (i <- 0 until PredictWidth) {
67    val inst = Wire(UInt(32.W))
68    val valid = Wire(Bool())
69    val pc = io.in.pc + (i << 1).U - Mux(io.prev.valid && (i.U === 0.U), 2.U, 0.U)
70
71    if (i==0) {
72      inst := Mux(io.prev.valid, Cat(data(15,0), io.prev.bits), data(31,0))
73      valid := true.B
74    } else if (i==1) {
75      inst := data(47,16)
76      valid := io.prev.valid || !(instsMask(0) && !isRVC(insts(0)))
77    } else if (i==PredictWidth-1) {
78      inst := Cat(0.U(16.W), data(i*16+15, i*16))
79      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
80    } else {
81      inst := data(i*16+31, i*16)
82      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
83    }
84
85    insts(i) := inst
86    instsRVC(i) := isRVC(inst)
87    instsMask(i) := mask(i) && valid
88    instsPC(i) := pc
89
90    val brType::isCall::isRet::Nil = brInfo(inst)
91    io.out.pd(i).isRVC := instsRVC(i)
92    io.out.pd(i).brType := brType
93    io.out.pd(i).isCall := isCall
94    io.out.pd(i).isRet := isRet
95    io.out.pd(i).excType := ExcType.notExc
96    io.out.instrs(i) := insts(i)
97    io.out.pc(i) := instsPC(i)
98
99  }
100  io.out.mask := instsMask.asUInt
101
102  for (i <- 0 until PredictWidth) {
103    XSDebug(true.B,
104      p"instr ${Hexdecimal(io.out.instrs(i))}, " +
105      p"mask ${Binary(instsMask(i))}, " +
106      p"pc ${Hexdecimal(io.out.pc(i))}, " +
107      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
108      p"brType ${Binary(io.out.pd(i).brType)}, " +
109      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
110      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
111    )
112  }
113}
114