xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision 28a7d001afbf5ec277b92034a17851fb5421d25d) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.backend.decode.isa.predecode.PreDecodeInst
7
8trait HasPdconst{ this: XSModule =>
9  val halfWidth = FetchWidth * 2
10  val groupAlign = log2Up(FetchWidth * 4)
11  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
12  def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
13  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
14  def brInfo(instr: UInt) = {
15    val rd = instr(11,7)
16    val rs = instr(19,15)
17    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
18    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
19    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
20    List(brType, isCall, isRet)
21  }
22}
23
24object BrType {
25  def notBr   = "b00".U
26  def branch  = "b01".U
27  def jal     = "b10".U
28  def jalr    = "b11".U
29  def apply() = UInt(2.W)
30}
31
32object ExcType {  //TODO:add exctype
33  def notExc = "b000".U
34  def apply() = UInt(3.W)
35}
36
37class PDEntry extends XSBundle{  // 8 bit
38  val isRVC   = Bool()
39  val brType  = UInt(2.W)
40  val isCall  = Bool()
41  val isRet   = Bool()
42  val excType = UInt(3.W)
43}
44
45class PDPacket extends XSBundle{
46  val pc = UInt(VAddrBits.W)
47  val inst = UInt(32.W)
48  val mask = Bool()
49  val pdEntry = new PDEntry
50}
51
52class ICacheResp extends XSBundle {
53  val fetchPc = UInt(VAddrBits.W)
54  val data = UInt((FetchWidth * 32).W)
55  val mask = UInt((FetchWidth * 2).W)
56}
57
58class PreDecode extends XSModule with HasPdconst{
59  val io = IO(new Bundle() {
60    val iCacheResp = Input(new ICacheResp)
61    val PreDecodeInfo = Output(Vec(halfWidth, new PDEntry))
62    val toIF4 = Output(Vec(halfWidth, new PDPacket))
63  })
64
65  val gpc = groupPC(io.iCacheResp.fetchPc)
66  val data = io.iCacheResp.data
67  val mask = io.iCacheResp.mask
68
69  val insts = Wire(Vec(halfWidth, UInt(32.W)))
70  val instsMask = Wire(Vec(halfWidth, Bool()))
71  val instsRVC = Wire(Vec(halfWidth,Bool()))
72  val instsPC = Wire(Vec(halfWidth, UInt(VAddrBits.W)))
73
74
75  val prevHalf = Reg(UInt(16.W))
76  val prevValid = RegInit(false.B)
77  val prevGPC = RegInit(0.U(VAddrBits.W))
78  val seriesPC = RegInit(true.B)  //two cacheline's gpc is continuous
79  val nextHalf = Wire(UInt(16.W))
80
81  for (i <- 0 until halfWidth) {
82    val inst = Wire(UInt(32.W))
83    val valid = Wire(Bool())
84    val pc = gpc + (i << 1).U - Mux(prevValid && (i.U === 0.U), 2.U, 0.U)
85    val brType::isCall::isRet::Nil = brInfo(inst)
86    if (i==0) {
87      inst := Mux(prevValid, Cat(data(15,0), prevHalf), data(31,0))
88      valid := true.B
89    } else if (i==1) {
90      inst := data(47,16)
91      valid := prevValid || !(instsMask(0) && !isRVC(insts(0)))
92    } else if (i==halfWidth-1) {
93      inst := Cat(0.U(16.W), data(i*16+15, i*16))
94      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
95    } else {
96      inst := data(i*16+31, i*16)
97      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
98    }
99
100    insts(i) := inst
101    instsRVC(i) := isRVC(inst)
102    instsMask(i) := mask(i) && valid
103    instsPC(i) := pc
104
105    io.PreDecodeInfo(i).isRVC := instsRVC(i)
106    io.PreDecodeInfo(i).brType := brType
107    io.PreDecodeInfo(i).isCall := isCall
108    io.PreDecodeInfo(i).isRet := isRet
109    io.PreDecodeInfo(i).excType := ExcType.notExc
110
111    io.toIF4(i).pdEntry := io.PreDecodeInfo(i)
112    io.toIF4(i).inst := insts(i)
113    io.toIF4(i).mask := instsMask(i)
114    io.toIF4(i).pc := instsPC(i)
115  }
116
117  //update
118  nextHalf := data(halfWidth*16-1, (halfWidth-1)*16)
119  prevHalf := nextHalf
120  seriesPC := 1.U === (gpc - prevGPC)(VAddrBits-1, groupAlign)
121  prevGPC := gpc
122  prevValid := !(instsMask(halfWidth-2) && !isRVC(insts(halfWidth-2))) && !isRVC(insts(halfWidth-1)) && seriesPC
123
124//  for (i <- 0 until halfWidth) {
125//    XSDebug(true.B,
126//      p"instr ${Binary(io.toIF4(i).inst)}, " +
127//      p"mask ${Binary(io.toIF4(i).mask)}, " +
128//      //p"pc ${Binary(io.toIF4(i).pc)}, " +
129//      p"isRVC ${Binary(io.PreDecodeInfo(i).isRVC)}, " +
130//      p"brType ${Binary(io.PreDecodeInfo(i).brType)}, " +
131//      p"isRet ${Binary(io.PreDecodeInfo(i).isRet)}, " +
132//      p"isCall ${Binary(io.PreDecodeInfo(i).isCall)}\n"
133//    )
134//  }
135//
136//  for (i <- 0 until halfWidth) {
137//    XSDebug(true.B,
138//      p"prevhalf ${Binary(prevHalf)}, " +
139//      p"prevvalid ${Binary(prevValid)}, " +
140//      p"seriesPC ${Binary(seriesPC)}\n"
141//    )
142//  }
143}
144