xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision 1854804ddc4c624f626112d707a8ac4aee24b0d4) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils.XSDebug
6import xiangshan._
7import xiangshan.backend.decode.isa.predecode.PreDecodeInst
8
9trait HasPdconst{ this: XSModule =>
10  // val groupAlign = log2Up(FetchWidth * 4)
11  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
12  // def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
13  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
14  def brInfo(instr: UInt) = {
15    val rd = instr(11,7)
16    val rs = instr(19,15)
17    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
18    val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
19    val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
20    List(brType, isCall, isRet)
21  }
22}
23
24object BrType {
25  def notBr   = "b00".U
26  def branch  = "b01".U
27  def jal     = "b10".U
28  def jalr    = "b11".U
29  def apply() = UInt(2.W)
30}
31
32object ExcType {  //TODO:add exctype
33  def notExc = "b000".U
34  def apply() = UInt(3.W)
35}
36
37class PreDecodeInfo extends XSBundle {  // 8 bit
38  val isRVC   = Bool()
39  val brType  = UInt(2.W)
40  val isCall  = Bool()
41  val isRet   = Bool()
42  val excType = UInt(3.W)
43}
44
45// class PDPacket extends PreDecodeInfo{
46//   val pc = UInt(VAddrBits.W)
47//   val inst = UInt(32.W)
48//   val mask = Bool()
49// }
50
51class PreDecodeResp extends XSBundle {
52  val instrs = Vec(PredictWidth, UInt(32.W))
53  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
54  val mask = UInt(PredictWidth.W)
55  val pd = Vec(PredictWidth, (new PreDecodeInfo))
56}
57
58// class ICacheResp extends XSBundle {
59//   val fetchPc = UInt(VAddrBits.W)
60//   val data = UInt((FetchWidth * 32).W)
61//   val mask = UInt((FetchWidth * 2).W)
62// }
63
64class FakeIcacheResp extends XSBundle {
65  val pc = UInt(VAddrBits.W)
66  // val data = Vec(FetchWidth, UInt(32.W))
67  val data = UInt((FetchWidth * 32).W)
68  val mask = UInt(PredictWidth.W)
69}
70
71class PreDecode extends XSModule with HasPdconst{
72  val io = IO(new Bundle() {
73    val in = Input(new FakeIcacheResp)
74    // val prevHalf = Input(UInt(16.W))
75    // val prevValid = Input(false.B)
76    val prev = ValidIO(UInt(16.W))
77
78    // val out = Output(Vec(PredictWidth, new PDPacket))
79    val out = Output(new PreDecodeResp)
80  })
81
82  // val gpc = groupPC(io.in.pc)
83  val data = io.in.data
84  val mask = io.in.mask
85
86  val insts = Wire(Vec(PredictWidth, UInt(32.W)))
87  val instsMask = Wire(Vec(PredictWidth, Bool()))
88  val instsRVC = Wire(Vec(PredictWidth,Bool()))
89  val instsPC = Wire(Vec(PredictWidth, UInt(VAddrBits.W)))
90  val nextHalf = Wire(UInt(16.W))
91
92  for (i <- 0 until PredictWidth) {
93    val inst = Wire(UInt(32.W))
94    val valid = Wire(Bool())
95    val pc = io.in.pc + (i << 1).U - Mux(io.prev.valid && (i.U === 0.U), 2.U, 0.U)
96
97    if (i==0) {
98      inst := Mux(io.prev.valid, Cat(data(15,0), io.prev.bits), data(31,0))
99      valid := true.B
100    } else if (i==1) {
101      inst := data(47,16)
102      valid := io.prev.valid || !(instsMask(0) && !isRVC(insts(0)))
103    } else if (i==PredictWidth-1) {
104      inst := Cat(0.U(16.W), data(i*16+15, i*16))
105      valid := !(instsMask(i-1) && !isRVC(insts(i-1)) || !isRVC(inst))
106    } else {
107      inst := data(i*16+31, i*16)
108      valid := !(instsMask(i-1) && !isRVC(insts(i-1)))
109    }
110
111    insts(i) := inst
112    instsRVC(i) := isRVC(inst)
113    instsMask(i) := mask(i) && valid
114    instsPC(i) := pc
115
116    val brType::isCall::isRet::Nil = brInfo(inst)
117    io.out.pd(i).isRVC := instsRVC(i)
118    io.out.pd(i).brType := brType
119    io.out.pd(i).isCall := isCall
120    io.out.pd(i).isRet := isRet
121    io.out.pd(i).excType := ExcType.notExc
122    io.out.instrs(i) := insts(i)
123    io.out.pc(i) := instsPC(i)
124
125  }
126  io.out.mask := instsMask.asUInt
127
128  for (i <- 0 until PredictWidth) {
129    XSDebug(true.B,
130      p"instr ${Hexdecimal(io.out.instrs(i))}, " +
131      p"mask ${Binary(instsMask(i))}, " +
132      p"pc ${Hexdecimal(io.out.pc(i))}, " +
133      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
134      p"brType ${Binary(io.out.pd(i).brType)}, " +
135      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
136      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
137    )
138  }
139}
140