1/**************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 **************************************************************************************** 16 */ 17 18 19package xiangshan.backend.fu.vector 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import utils.XSError 24import xiangshan.backend.fu.FunctionUnit 25import yunsuan.vector.VectorIntAdder 26import yunsuan.{VipuType, VectorElementFormat} 27 28class VIPU(implicit p: Parameters) extends FunctionUnit(/*len = 128/VLEN*/) { 29 XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VipuType.dummy, "VIPU OpType not supported") 30 31 val uop = io.in.bits.uop 32 33 val AdderWidth = 64 34 val NumAdder = 1 // TODO: replace with VLEN/AdderWidth when rf ready 35 val adder = Seq.fill(NumAdder)(Module(new VectorIntAdder())) 36 for(i <- 0 until NumAdder) { 37 adder(i).io.in_0 := io.in.bits.src(0)(AdderWidth*(i+1)-1, AdderWidth*i) 38 adder(i).io.in_1 := io.in.bits.src(1)(AdderWidth*(i+1)-1, AdderWidth*i) 39 adder(i).io.int_format := VectorElementFormat.d // TODO 40 adder(i).io.op_code := uop.ctrl.fuOpType 41 adder(i).io.carry_or_borrow_in := DontCare 42 } 43 val adder_result = VecInit(adder.map(_.io.out)).asUInt 44 45 io.out.bits.data := adder_result 46 io.out.bits.uop := io.in.bits.uop 47 io.out.valid := io.in.valid 48 io.in.ready := io.out.ready 49}