1///**************************************************************************************** 2// * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3// * Copyright (c) 2020-2021 Peng Cheng Laboratory 4// * 5// * XiangShan is licensed under Mulan PSL v2. 6// * You can use this software according to the terms and conditions of the Mulan PSL v2. 7// * You may obtain a copy of Mulan PSL v2 at: 8// * http://license.coscl.org.cn/MulanPSL2 9// * 10// * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11// * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12// * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13// * 14// * See the Mulan PSL v2 for more details. 15// **************************************************************************************** 16// */ 17// 18// 19//package xiangshan.backend.fu.vector 20// 21//import org.chipsalliance.cde.config.Parameters 22//import chisel3._ 23//import chisel3.util._ 24//import utils._ 25//import utility._ 26//import yunsuan.vector.alu.{VAluOpcode, VIAlu} 27//import yunsuan.{VectorElementFormat, VipuType} 28//import xiangshan.{SelImm, SrcType, UopSplitType, XSCoreParamsKey, XSModule,FuType} 29// 30//import scala.collection.Seq 31// 32//class VIAluDecodeResultBundle extends Bundle { 33// val opcode = UInt(6.W) 34// val srcType2 = UInt(4.W) 35// val srcType1 = UInt(4.W) 36// val vdType = UInt(4.W) 37//} 38// 39//class VIAluDecoder (implicit p: Parameters) extends XSModule { 40// val io = IO(new Bundle{ 41// val in = Input(new Bundle{ 42// val fuOpType = UInt(8.W) 43// val sew = UInt(2.W) 44// }) 45// val out = Output(new VIAluDecodeResultBundle) 46// }) 47// 48// // u 00 s 01 f 10 mask 1111 49// val uSew = Cat(0.U(2.W), io.in.sew) 50// val uSew2 = Cat(0.U(2.W), (io.in.sew+1.U)) 51// val uSewf2 = Cat(0.U(2.W), (io.in.sew-1.U)) 52// val uSewf4 = Cat(0.U(2.W), (io.in.sew-2.U)) 53// val uSewf8 = Cat(0.U(2.W), (io.in.sew-3.U)) 54// val sSew = Cat(1.U(2.W), io.in.sew) 55// val sSew2 = Cat(1.U(2.W), (io.in.sew+1.U)) 56// val sSewf2 = Cat(1.U(2.W), (io.in.sew - 1.U)) 57// val sSewf4 = Cat(1.U(2.W), (io.in.sew - 2.U)) 58// val sSewf8 = Cat(1.U(2.W), (io.in.sew - 3.U)) 59// val mask = "b1111".U(4.W) 60// 61// val out = LookupTree(io.in.fuOpType, List( 62// // --------------------- opcode srcType2 1 vdType 63// VipuType.vredsum_vs -> Cat(VAluOpcode.vredsum, uSew, uSew, uSew).asUInt, 64// VipuType.vredmaxu_vs -> Cat(VAluOpcode.vredmax, uSew, uSew, uSew).asUInt, 65// VipuType.vredmax_vs -> Cat(VAluOpcode.vredmax, sSew, sSew, sSew).asUInt, 66// VipuType.vredminu_vs -> Cat(VAluOpcode.vredmin, uSew, uSew, uSew).asUInt, 67// VipuType.vredmin_vs -> Cat(VAluOpcode.vredmin, sSew, sSew, sSew).asUInt, 68// VipuType.vredand_vs -> Cat(VAluOpcode.vredand, uSew, uSew, uSew).asUInt, 69// VipuType.vredor_vs -> Cat(VAluOpcode.vredor, uSew, uSew, uSew).asUInt, 70// VipuType.vredxor_vs -> Cat(VAluOpcode.vredxor, uSew, uSew, uSew).asUInt, 71// 72// VipuType.vwredsumu_vs -> Cat(VAluOpcode.vredsum, uSew, uSew, uSew2).asUInt, 73// VipuType.vwredsum_vs -> Cat(VAluOpcode.vredsum, sSew, sSew, sSew2).asUInt, 74// 75// VipuType.vcpop_m -> Cat(VAluOpcode.vcpop, mask, mask, uSew).asUInt, 76// VipuType.vfirst_m -> Cat(VAluOpcode.vfirst, mask, mask, uSew).asUInt, 77// VipuType.vmsbf_m -> Cat(VAluOpcode.vmsbf, mask, mask, mask).asUInt, 78// VipuType.vmsif_m -> Cat(VAluOpcode.vmsif, mask, mask, mask).asUInt, 79// VipuType.vmsof_m -> Cat(VAluOpcode.vmsof, mask, mask, mask).asUInt, 80// 81// VipuType.viota_m -> Cat(VAluOpcode.viota, uSew, uSew, uSew).asUInt, 82// VipuType.vid_v -> Cat(VAluOpcode.vid, uSew, uSew, uSew).asUInt 83// 84// )).asTypeOf(new VIAluDecodeResultBundle) 85// 86// io.out <> out 87//} 88// 89//class VIAluWrapper(implicit p: Parameters) extends VPUDataModule{ 90// 91// needReverse := false.B 92// needClearMask := false.B 93// 94// // connect VIAlu 95// val decoder = Module(new VIAluDecoder) 96// val vialu = Module(new VIAlu) 97// decoder.io.in.fuOpType := in.uop.ctrl.fuOpType 98// decoder.io.in.sew := in.uop.ctrl.vconfig.vtype.vsew(1,0) 99// 100// vialu.io.in.bits.opcode := decoder.io.out.opcode.asTypeOf(vialu.io.in.bits.opcode.cloneType) 101// vialu.io.in.bits.info.vm := in.uop.ctrl.vm 102// vialu.io.in.bits.info.ma := in.uop.ctrl.vconfig.vtype.vma 103// vialu.io.in.bits.info.ta := in.uop.ctrl.vconfig.vtype.vta 104// vialu.io.in.bits.info.vlmul := in.uop.ctrl.vconfig.vtype.vlmul 105// vialu.io.in.bits.info.vl := in.uop.ctrl.vconfig.vl 106// 107// vialu.io.in.bits.info.vstart := vstart // TODO : 108// vialu.io.in.bits.info.uopIdx := in.uop.ctrl.uopIdx 109// 110// vialu.io.in.bits.info.vxrm := vxrm 111// vialu.io.in.bits.srcType(0) := decoder.io.out.srcType2 112// vialu.io.in.bits.srcType(1) := decoder.io.out.srcType1 113// vialu.io.in.bits.vdType := decoder.io.out.vdType 114// val lmul = MuxLookup(in.uop.ctrl.vconfig.vtype.vlmul , 1.U(4.W), Array( 115// "b001".U -> 2.U, 116// "b010".U -> 4.U, 117// "b011".U -> 8.U 118// )) 119// val needClearVs1 = (VipuType.vcpop_m === in.uop.ctrl.fuOpType && in.uop.ctrl.uopIdx === 0.U) || 120// (VipuType.viota_m === in.uop.ctrl.fuOpType && in.uop.ctrl.uopIdx(log2Up(MaxUopSize)-1,1) === 0.U) || 121// (VipuType.vid_v === in.uop.ctrl.fuOpType && in.uop.ctrl.uopIdx(log2Up(MaxUopSize)-1,1) === 0.U) // dirty code TODO: inset into IAlu 122// val needShiftVs1 = (VipuType.vwredsumu_vs === in.uop.ctrl.fuOpType || VipuType.vwredsum_vs === in.uop.ctrl.fuOpType) && 123// in.uop.ctrl.uopIdx < lmul 124// vialu.io.in.bits.vs1 := Mux1H(Seq( 125// needClearVs1 -> 0.U, 126// needShiftVs1 -> SignExt(vs1(127,64), 128), 127// ((!needClearVs1)&&(!needShiftVs1)) -> vs1 128// )) 129// vialu.io.in.bits.vs2 := vs2 130// vialu.io.in.bits.old_vd := in.src(2) 131// vialu.io.in.bits.mask := mask 132// 133// vialu.io.in.valid := io.in.valid 134// 135// // connect io 136// io.out.bits.data := vialu.io.out.bits.vd 137// vxsat := vialu.io.out.bits.vxsat 138// io.out.valid := vialu.io.out.valid 139//} 140// 141//class VIPU(implicit p: Parameters) extends VPUSubModule(p(XSCoreParamsKey).VLEN) { 142// XSError(io.in.valid && io.in.bits.uop.ctrl.fuOpType === VipuType.dummy, "VIPU OpType not supported") 143// override val dataModule = Seq(Module(new VIAluWrapper)) 144// override val select = Seq( 145// io.in.bits.uop.ctrl.fuType === FuType.vipu 146// ) 147// connectDataModule 148//} 149