1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend._ 25import xiangshan.backend.decode.ImmUnion 26import xiangshan.backend.decode.isa._ 27 28trait HasRedirectOut { this: XSModule => 29 val redirectOutValid = IO(Output(Bool())) 30 val redirectOut = IO(Output(new Redirect)) 31} 32 33class JumpDataModule(implicit p: Parameters) extends XSModule { 34 val io = IO(new Bundle() { 35 val src = Input(UInt(XLEN.W)) 36 val pc = Input(UInt(XLEN.W)) // sign-ext to XLEN 37 val immMin = Input(UInt(ImmUnion.maxLen.W)) 38 val func = Input(FuOpType()) 39 val isRVC = Input(Bool()) 40 val result, target = Output(UInt(XLEN.W)) 41 val isAuipc = Output(Bool()) 42 }) 43 val (src1, pc, immMin, func, isRVC) = (io.src, io.pc, io.immMin, io.func, io.isRVC) 44 45 val isJalr = JumpOpType.jumpOpisJalr(func) 46 val isAuipc = JumpOpType.jumpOpisAuipc(func) 47 val offset = SignExt(ParallelMux(Seq( 48 isJalr -> ImmUnion.I.toImm32(immMin), 49 isAuipc -> ImmUnion.U.toImm32(immMin), 50 !(isJalr || isAuipc) -> ImmUnion.J.toImm32(immMin) 51 )), XLEN) 52 53 val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 54 val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 55 56 io.target := target 57 io.result := Mux(JumpOpType.jumpOpisAuipc(func), target, snpc) 58 io.isAuipc := isAuipc 59} 60 61class Jump(implicit p: Parameters) extends FUWithRedirect { 62 63 val (src1, jalr_target, pc, immMin, func, uop) = ( 64 io.in.bits.src(0), 65 io.in.bits.src(1)(VAddrBits - 1, 0), 66 SignExt(io.in.bits.uop.cf.pc, XLEN), 67 io.in.bits.uop.ctrl.imm, 68 io.in.bits.uop.ctrl.fuOpType, 69 io.in.bits.uop 70 ) 71 72 val redirectHit = uop.roqIdx.needFlush(io.redirectIn, io.flushIn) 73 val valid = io.in.valid 74 val isRVC = uop.cf.pd.isRVC 75 76 val jumpDataModule = Module(new JumpDataModule) 77 jumpDataModule.io.src := src1 78 jumpDataModule.io.pc := pc 79 jumpDataModule.io.immMin := immMin 80 jumpDataModule.io.func := func 81 jumpDataModule.io.isRVC := isRVC 82 83 redirectOutValid := valid && !jumpDataModule.io.isAuipc 84 redirectOut := DontCare 85 redirectOut.level := RedirectLevel.flushAfter 86 redirectOut.roqIdx := uop.roqIdx 87 redirectOut.ftqIdx := uop.cf.ftqPtr 88 redirectOut.ftqOffset := uop.cf.ftqOffset 89 redirectOut.cfiUpdate.predTaken := true.B 90 redirectOut.cfiUpdate.taken := true.B 91 redirectOut.cfiUpdate.target := jumpDataModule.io.target 92 redirectOut.cfiUpdate.isMisPred := jumpDataModule.io.target(VAddrBits - 1, 0) =/= jalr_target || !uop.cf.pred_taken 93 94 io.in.ready := io.out.ready 95 io.out.valid := valid 96 io.out.bits.uop <> io.in.bits.uop 97 io.out.bits.data := jumpDataModule.io.result 98 99 // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 100 XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d)\n", 101 io.in.valid, 102 io.in.ready, 103 io.out.valid, 104 io.out.ready, 105 io.redirectIn.valid, 106 io.redirectIn.bits.level, 107 redirectHit 108 ) 109} 110