1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend._ 25import xiangshan.backend.decode.ImmUnion 26import xiangshan.backend.decode.isa._ 27 28trait HasRedirectOut { this: XSModule => 29 val redirectOutValid = IO(Output(Bool())) 30 val redirectOut = IO(Output(new Redirect)) 31} 32 33class JumpDataModule(implicit p: Parameters) extends XSModule { 34 val io = IO(new Bundle() { 35 val src = Input(UInt(XLEN.W)) 36 val pc = Input(UInt(XLEN.W)) // sign-ext to XLEN 37 val immMin = Input(UInt(ImmUnion.maxLen.W)) 38 val func = Input(FuOpType()) 39 val isRVC = Input(Bool()) 40 val result, target = Output(UInt(XLEN.W)) 41 val isAuipc = Output(Bool()) 42 }) 43 val (src1, pc, immMin, func, isRVC) = (io.src, io.pc, io.immMin, io.func, io.isRVC) 44 45 val isJalr = JumpOpType.jumpOpisJalr(func) 46 val isAuipc = JumpOpType.jumpOpisAuipc(func) 47 val offset = SignExt(ParallelMux(Seq( 48 isJalr -> ImmUnion.I.toImm32(immMin), 49 isAuipc -> ImmUnion.U.toImm32(immMin), 50 !(isJalr || isAuipc) -> ImmUnion.J.toImm32(immMin) 51 )), XLEN) 52 53 val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 54 val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 55 56 // RISC-V spec for JALR: 57 // The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, 58 // then setting the least-significant bit of the result to zero. 59 io.target := Cat(target(XLEN - 1, 1), false.B) 60 io.result := Mux(JumpOpType.jumpOpisAuipc(func), target, snpc) 61 io.isAuipc := isAuipc 62} 63 64class Jump(implicit p: Parameters) extends FUWithRedirect { 65 66 val (src1, jalr_target, pc, immMin, func, uop) = ( 67 io.in.bits.src(0), 68 io.in.bits.src(1)(VAddrBits - 1, 0), 69 SignExt(io.in.bits.uop.cf.pc, XLEN), 70 io.in.bits.uop.ctrl.imm, 71 io.in.bits.uop.ctrl.fuOpType, 72 io.in.bits.uop 73 ) 74 75 val redirectHit = uop.robIdx.needFlush(io.redirectIn) 76 val valid = io.in.valid 77 val isRVC = uop.cf.pd.isRVC 78 79 val jumpDataModule = Module(new JumpDataModule) 80 jumpDataModule.io.src := src1 81 jumpDataModule.io.pc := pc 82 jumpDataModule.io.immMin := immMin 83 jumpDataModule.io.func := func 84 jumpDataModule.io.isRVC := isRVC 85 86 redirectOutValid := valid && !jumpDataModule.io.isAuipc 87 redirectOut := DontCare 88 redirectOut.level := RedirectLevel.flushAfter 89 redirectOut.robIdx := uop.robIdx 90 redirectOut.ftqIdx := uop.cf.ftqPtr 91 redirectOut.ftqOffset := uop.cf.ftqOffset 92 redirectOut.cfiUpdate.predTaken := true.B 93 redirectOut.cfiUpdate.taken := true.B 94 redirectOut.cfiUpdate.target := jumpDataModule.io.target 95 redirectOut.cfiUpdate.isMisPred := jumpDataModule.io.target(VAddrBits - 1, 0) =/= jalr_target || !uop.cf.pred_taken 96 redirectOut.debug_runahead_checkpoint_id := uop.debugInfo.runahead_checkpoint_id 97 98 io.in.ready := io.out.ready 99 io.out.valid := valid 100 io.out.bits.uop <> io.in.bits.uop 101 io.out.bits.data := jumpDataModule.io.result 102 103 // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 104 XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d)\n", 105 io.in.valid, 106 io.in.ready, 107 io.out.valid, 108 io.out.ready, 109 io.redirectIn.valid, 110 io.redirectIn.bits.level, 111 redirectHit 112 ) 113} 114