1package xiangshan.backend.fu 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils._ 7import xiangshan.backend._ 8import xiangshan.backend.fu.FunctionUnit._ 9 10class Jump extends FunctionUnit(jmpCfg){ 11 val io = IO(new ExuIO) 12 13 val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop) 14 15 val redirectHit = uop.brTag.needFlush(io.redirect) 16 val valid = iovalid && !redirectHit 17 18 val isRVC = uop.cf.isRVC 19 val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U) 20 val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 21 22 io.out.bits.redirectValid := valid 23 io.out.bits.redirect.target := target 24 io.out.bits.redirect.brTag := uop.brTag 25 io.out.bits.redirect.isException := false.B 26 io.out.bits.redirect.roqIdx := uop.roqIdx 27 28 // Output 29 val res = pcDelaySlot 30 31 io.in.ready := io.out.ready 32 io.out.valid := valid // TODO: CSR/MOU/FMV may need change it 33 io.out.bits.uop <> io.in.bits.uop 34 io.out.bits.data := res 35 36 io.dmem <> DontCare 37 io.out.bits.debug <> DontCare 38 39 // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 40 XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x\n", 41 io.in.valid, 42 io.in.ready, 43 io.out.valid, 44 io.out.ready, 45 io.redirect.valid, 46 io.redirect.bits.isException, 47 redirectHit, 48 io.redirect.bits.brTag.value 49 ) 50 XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 51} 52