1cafb3558SLinJiaweipackage xiangshan.backend.fu 2cafb3558SLinJiawei 3cafb3558SLinJiaweiimport chisel3._ 4cafb3558SLinJiaweiimport chisel3.util._ 5cafb3558SLinJiaweiimport xiangshan._ 6b9fd1892SLinJiaweiimport utils._ 7cafb3558SLinJiaweiimport xiangshan.backend._ 8cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._ 9ccd5d342SGouLingruiimport xiangshan.backend.decode.isa._ 10cafb3558SLinJiawei 11*e18c367fSLinJiaweitrait HasRedirectOut { this: RawModule => 12*e18c367fSLinJiawei val redirectOutValid = IO(Output(Bool())) 13*e18c367fSLinJiawei val redirectOut = IO(Output(new Redirect)) 14*e18c367fSLinJiawei val brUpdate = IO(Output(new BranchUpdateInfo)) 15b2e234ebSLinJiawei} 16cafb3558SLinJiawei 17*e18c367fSLinJiaweiclass Jump extends FunctionUnit( 18*e18c367fSLinJiawei FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true) 19*e18c367fSLinJiawei) with HasRedirectOut { 20cafb3558SLinJiawei 21*e18c367fSLinJiawei val (src1, offset, func, pc, uop) = ( 22b2e234ebSLinJiawei io.in.bits.src(0), 23b2e234ebSLinJiawei io.in.bits.uop.ctrl.imm, 24b2e234ebSLinJiawei io.in.bits.uop.ctrl.fuOpType, 25b2e234ebSLinJiawei SignExt(io.in.bits.uop.cf.pc, AddrBits), 26b2e234ebSLinJiawei io.in.bits.uop 27b2e234ebSLinJiawei ) 28b2e234ebSLinJiawei 293136ee6aSLinJiawei val redirectHit = uop.roqIdx.needFlush(io.redirectIn) 30*e18c367fSLinJiawei val valid = io.in.valid && !redirectHit 31cafb3558SLinJiawei 32608ba82cSzhanglinjuan val isRVC = uop.cf.brUpdate.pd.isRVC 33*e18c367fSLinJiawei val snpc = Mux(isRVC, pc + 2.U, pc + 4.U) 34cafb3558SLinJiawei val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 35cafb3558SLinJiawei 36*e18c367fSLinJiawei redirectOutValid := valid 37b2e234ebSLinJiawei redirectOut.pc := uop.cf.pc 38b2e234ebSLinJiawei redirectOut.target := target 39b2e234ebSLinJiawei redirectOut.brTag := uop.brTag 40b2e234ebSLinJiawei redirectOut.isException := false.B 41b2e234ebSLinJiawei redirectOut.isFlushPipe := false.B 42b2e234ebSLinJiawei redirectOut.isMisPred := DontCare // check this in brq 43b2e234ebSLinJiawei redirectOut.isReplay := false.B 44b2e234ebSLinJiawei redirectOut.roqIdx := uop.roqIdx 45b2e234ebSLinJiawei 46b2e234ebSLinJiawei brUpdate := uop.cf.brUpdate 47b2e234ebSLinJiawei brUpdate.pc := uop.cf.pc 48b2e234ebSLinJiawei brUpdate.target := target 49b2e234ebSLinJiawei brUpdate.brTarget := target // DontCare 50b2e234ebSLinJiawei brUpdate.taken := true.B 51b2e6921eSLinJiawei 52cafb3558SLinJiawei // Output 53*e18c367fSLinJiawei val res = snpc 54cafb3558SLinJiawei 55cafb3558SLinJiawei io.in.ready := io.out.ready 56*e18c367fSLinJiawei io.out.valid := valid 57cafb3558SLinJiawei io.out.bits.uop <> io.in.bits.uop 58cafb3558SLinJiawei io.out.bits.data := res 59cafb3558SLinJiawei 60cafb3558SLinJiawei // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 6145a56a29SZhangZifei XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d %d) brTag:%x\n", 6212ff7156SLinJiawei io.in.valid, 6312ff7156SLinJiawei io.in.ready, 6412ff7156SLinJiawei io.out.valid, 6512ff7156SLinJiawei io.out.ready, 66b2e234ebSLinJiawei io.redirectIn.valid, 67b2e234ebSLinJiawei io.redirectIn.bits.isException, 68b2e234ebSLinJiawei io.redirectIn.bits.isFlushPipe, 6912ff7156SLinJiawei redirectHit, 70b2e234ebSLinJiawei io.redirectIn.bits.brTag.value 7112ff7156SLinJiawei ) 7212ff7156SLinJiawei XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 73cafb3558SLinJiawei} 74