1*cafb3558SLinJiaweipackage xiangshan.backend.fu 2*cafb3558SLinJiawei 3*cafb3558SLinJiaweiimport chisel3._ 4*cafb3558SLinJiaweiimport chisel3.util._ 5*cafb3558SLinJiaweiimport xiangshan._ 6*cafb3558SLinJiaweiimport xiangshan.utils._ 7*cafb3558SLinJiaweiimport xiangshan.backend._ 8*cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._ 9*cafb3558SLinJiawei 10*cafb3558SLinJiaweiclass Jump extends FunctionUnit(jmpCfg){ 11*cafb3558SLinJiawei val io = IO(new ExuIO) 12*cafb3558SLinJiawei 13*cafb3558SLinJiawei override def toString: String = "Bru" 14*cafb3558SLinJiawei 15*cafb3558SLinJiawei val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop) 16*cafb3558SLinJiawei 17*cafb3558SLinJiawei val redirectHit = uop.brTag.needFlush(io.redirect) 18*cafb3558SLinJiawei val valid = iovalid && !redirectHit 19*cafb3558SLinJiawei 20*cafb3558SLinJiawei val isCSR = BRUOpType.isCSR(func) 21*cafb3558SLinJiawei val isFMV = BRUOpType.isFMV(func) 22*cafb3558SLinJiawei val isMOU = BRUOpType.isMOU(func) 23*cafb3558SLinJiawei val isJUMP = BRUOpType.isJUMP(func) 24*cafb3558SLinJiawei 25*cafb3558SLinJiawei // JUMP 26*cafb3558SLinJiawei val isRVC = uop.cf.isRVC 27*cafb3558SLinJiawei val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U) 28*cafb3558SLinJiawei val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 29*cafb3558SLinJiawei 30*cafb3558SLinJiawei io.out.bits.redirectValid := valid && isJUMP 31*cafb3558SLinJiawei io.out.bits.redirect.target := target 32*cafb3558SLinJiawei io.out.bits.redirect.brTag := uop.brTag 33*cafb3558SLinJiawei io.out.bits.redirect.isException := false.B 34*cafb3558SLinJiawei io.out.bits.redirect.roqIdx := uop.roqIdx 35*cafb3558SLinJiawei io.out.bits.redirect.freelistAllocPtr := uop.freelistAllocPtr 36*cafb3558SLinJiawei 37*cafb3558SLinJiawei // Output 38*cafb3558SLinJiawei val resCSR = WireInit(0.U(XLEN.W)) // TODO: implement it 39*cafb3558SLinJiawei val resFMV = WireInit(0.U(XLEN.W)) // TODO: implement it 40*cafb3558SLinJiawei val resMOU = WireInit(0.U(XLEN.W)) // TODO: implement it 41*cafb3558SLinJiawei val resJMP = pcDelaySlot 42*cafb3558SLinJiawei val res = ParallelMux( 43*cafb3558SLinJiawei VecInit(isCSR, isFMV, isMOU, isJUMP) zip 44*cafb3558SLinJiawei VecInit(resCSR, resFMV, resMOU, resJMP) 45*cafb3558SLinJiawei ) 46*cafb3558SLinJiawei 47*cafb3558SLinJiawei io.in.ready := io.out.ready 48*cafb3558SLinJiawei io.out.valid := valid // TODO: CSR/MOU/FMV may need change it 49*cafb3558SLinJiawei io.out.bits.uop <> io.in.bits.uop 50*cafb3558SLinJiawei io.out.bits.data := res 51*cafb3558SLinJiawei 52*cafb3558SLinJiawei // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 53*cafb3558SLinJiawei XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x\n", 54*cafb3558SLinJiawei io.in.valid, io.in.ready, io.out.valid, io.out.ready, io.redirect.valid, io.redirect.bits.isException, redirectHit, io.redirect.bits.brTag.value) 55*cafb3558SLinJiawei XSDebug(io.in.valid && isCSR, "src1:%x offset:%x func:%b type:CSR pc:%x\n", src1, offset, func, pc) 56*cafb3558SLinJiawei XSDebug(io.in.valid && isFMV, "src1:%x offset:%x func:%b type:FMV pc:%x\n", src1, offset, func, pc) 57*cafb3558SLinJiawei XSDebug(io.in.valid && isMOU, "src1:%x offset:%x func:%b type:MOU pc:%x\n", src1, offset, func, pc) 58*cafb3558SLinJiawei XSDebug(io.in.valid && isJUMP, "src1:%x offset:%x func:%b type:JUMP pc:%x\n", src1, offset, func, pc) 59*cafb3558SLinJiawei XSDebug(io.in.valid, "Res:%x` CsrRes:%x FMV:%x Mou:%x Jmp:%x\n", res, resCSR, resFMV, resMOU, resJMP) 60*cafb3558SLinJiawei} 61