1cafb3558SLinJiaweipackage xiangshan.backend.fu 2cafb3558SLinJiawei 3cafb3558SLinJiaweiimport chisel3._ 4cafb3558SLinJiaweiimport chisel3.util._ 5cafb3558SLinJiaweiimport xiangshan._ 6b9fd1892SLinJiaweiimport utils._ 7cafb3558SLinJiaweiimport xiangshan.backend._ 8cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._ 9ccd5d342SGouLingruiimport xiangshan.backend.decode.isa._ 10cafb3558SLinJiawei 11*b2e234ebSLinJiaweiclass RedirectOut extends XSBundle { 12*b2e234ebSLinJiawei val redirectValid = Bool() 13*b2e234ebSLinJiawei val redirect = new Redirect 14*b2e234ebSLinJiawei val brUpdate = new BranchUpdateInfo 15*b2e234ebSLinJiawei} 16cafb3558SLinJiawei 17*b2e234ebSLinJiaweiclass Jump extends FunctionUnit(jmpCfg, extOut = new RedirectOut) { 18cafb3558SLinJiawei 19*b2e234ebSLinJiawei val (iovalid, src1, offset, func, pc, uop) = ( 20*b2e234ebSLinJiawei io.in.valid, 21*b2e234ebSLinJiawei io.in.bits.src(0), 22*b2e234ebSLinJiawei io.in.bits.uop.ctrl.imm, 23*b2e234ebSLinJiawei io.in.bits.uop.ctrl.fuOpType, 24*b2e234ebSLinJiawei SignExt(io.in.bits.uop.cf.pc, AddrBits), 25*b2e234ebSLinJiawei io.in.bits.uop 26*b2e234ebSLinJiawei ) 27*b2e234ebSLinJiawei 28*b2e234ebSLinJiawei val redirectHit = uop.needFlush(io.redirectIn) 29cafb3558SLinJiawei val valid = iovalid && !redirectHit 30cafb3558SLinJiawei 31608ba82cSzhanglinjuan val isRVC = uop.cf.brUpdate.pd.isRVC 32cafb3558SLinJiawei val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U) 33cafb3558SLinJiawei val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 34cafb3558SLinJiawei 35*b2e234ebSLinJiawei val redirectOut = io.out.bits.ext.get.redirect 36*b2e234ebSLinJiawei val brUpdate = io.out.bits.ext.get.brUpdate 37cafb3558SLinJiawei 38*b2e234ebSLinJiawei io.out.bits.ext.get.redirectValid := valid 39*b2e234ebSLinJiawei redirectOut.pc := uop.cf.pc 40*b2e234ebSLinJiawei redirectOut.target := target 41*b2e234ebSLinJiawei redirectOut.brTag := uop.brTag 42*b2e234ebSLinJiawei redirectOut.isException := false.B 43*b2e234ebSLinJiawei redirectOut.isFlushPipe := false.B 44*b2e234ebSLinJiawei redirectOut.isMisPred := DontCare // check this in brq 45*b2e234ebSLinJiawei redirectOut.isReplay := false.B 46*b2e234ebSLinJiawei redirectOut.roqIdx := uop.roqIdx 47*b2e234ebSLinJiawei 48*b2e234ebSLinJiawei brUpdate := uop.cf.brUpdate 49*b2e234ebSLinJiawei brUpdate.pc := uop.cf.pc 50*b2e234ebSLinJiawei brUpdate.target := target 51*b2e234ebSLinJiawei brUpdate.brTarget := target // DontCare 52*b2e234ebSLinJiawei brUpdate.taken := true.B 53608ba82cSzhanglinjuan // io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U //TODO: consider RVC 54b2e6921eSLinJiawei 55cafb3558SLinJiawei // Output 5612ff7156SLinJiawei val res = pcDelaySlot 57cafb3558SLinJiawei 58cafb3558SLinJiawei io.in.ready := io.out.ready 59cafb3558SLinJiawei io.out.valid := valid // TODO: CSR/MOU/FMV may need change it 60cafb3558SLinJiawei io.out.bits.uop <> io.in.bits.uop 61cafb3558SLinJiawei io.out.bits.data := res 62cafb3558SLinJiawei 63cafb3558SLinJiawei // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 6445a56a29SZhangZifei XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d %d) brTag:%x\n", 6512ff7156SLinJiawei io.in.valid, 6612ff7156SLinJiawei io.in.ready, 6712ff7156SLinJiawei io.out.valid, 6812ff7156SLinJiawei io.out.ready, 69*b2e234ebSLinJiawei io.redirectIn.valid, 70*b2e234ebSLinJiawei io.redirectIn.bits.isException, 71*b2e234ebSLinJiawei io.redirectIn.bits.isFlushPipe, 7212ff7156SLinJiawei redirectHit, 73*b2e234ebSLinJiawei io.redirectIn.bits.brTag.value 7412ff7156SLinJiawei ) 7512ff7156SLinJiawei XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 76cafb3558SLinJiawei} 77