1cafb3558SLinJiaweipackage xiangshan.backend.fu 2cafb3558SLinJiawei 3cafb3558SLinJiaweiimport chisel3._ 4cafb3558SLinJiaweiimport chisel3.util._ 5cafb3558SLinJiaweiimport xiangshan._ 6b9fd1892SLinJiaweiimport utils._ 7cafb3558SLinJiaweiimport xiangshan.backend._ 8cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._ 9ccd5d342SGouLingruiimport xiangshan.backend.decode.isa._ 10cafb3558SLinJiawei 11cafb3558SLinJiaweiclass Jump extends FunctionUnit(jmpCfg){ 12cafb3558SLinJiawei val io = IO(new ExuIO) 13cafb3558SLinJiawei 14cafb3558SLinJiawei val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop) 15cafb3558SLinJiawei 16*691af0f8SLinJiawei val redirectHit = uop.needFlush(io.redirect) 17cafb3558SLinJiawei val valid = iovalid && !redirectHit 18cafb3558SLinJiawei 19b2e6921eSLinJiawei val isRVC = uop.cf.brUpdate.isRVC 20cafb3558SLinJiawei val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U) 21cafb3558SLinJiawei val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 22cafb3558SLinJiawei 2312ff7156SLinJiawei io.out.bits.redirectValid := valid 24ccd5d342SGouLingrui io.out.bits.redirect.pc := uop.cf.pc 25cafb3558SLinJiawei io.out.bits.redirect.target := target 26cafb3558SLinJiawei io.out.bits.redirect.brTag := uop.brTag 27cafb3558SLinJiawei io.out.bits.redirect.isException := false.B 28b2e6921eSLinJiawei io.out.bits.redirect.isMisPred := DontCare // check this in brq 29b2e6921eSLinJiawei io.out.bits.redirect.isReplay := false.B 30cafb3558SLinJiawei io.out.bits.redirect.roqIdx := uop.roqIdx 31cafb3558SLinJiawei 32b2e6921eSLinJiawei io.out.bits.brUpdate := uop.cf.brUpdate 33b2e6921eSLinJiawei io.out.bits.brUpdate.brTarget := target // DontCare 34b2e6921eSLinJiawei io.out.bits.brUpdate.btbType := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable) 35b2e6921eSLinJiawei io.out.bits.brUpdate.taken := true.B 36b2e6921eSLinJiawei io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U //TODO: consider RVC 37b2e6921eSLinJiawei 38cafb3558SLinJiawei // Output 3912ff7156SLinJiawei val res = pcDelaySlot 40cafb3558SLinJiawei 41cafb3558SLinJiawei io.in.ready := io.out.ready 42cafb3558SLinJiawei io.out.valid := valid // TODO: CSR/MOU/FMV may need change it 43cafb3558SLinJiawei io.out.bits.uop <> io.in.bits.uop 44cafb3558SLinJiawei io.out.bits.data := res 45cafb3558SLinJiawei 4612ff7156SLinJiawei io.dmem <> DontCare 4712ff7156SLinJiawei io.out.bits.debug <> DontCare 4812ff7156SLinJiawei 49cafb3558SLinJiawei // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 50cafb3558SLinJiawei XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x\n", 5112ff7156SLinJiawei io.in.valid, 5212ff7156SLinJiawei io.in.ready, 5312ff7156SLinJiawei io.out.valid, 5412ff7156SLinJiawei io.out.ready, 5512ff7156SLinJiawei io.redirect.valid, 5612ff7156SLinJiawei io.redirect.bits.isException, 5712ff7156SLinJiawei redirectHit, 5812ff7156SLinJiawei io.redirect.bits.brTag.value 5912ff7156SLinJiawei ) 6012ff7156SLinJiawei XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 61cafb3558SLinJiawei} 62