1cafb3558SLinJiaweipackage xiangshan.backend.fu 2cafb3558SLinJiawei 3cafb3558SLinJiaweiimport chisel3._ 4cafb3558SLinJiaweiimport chisel3.util._ 5cafb3558SLinJiaweiimport xiangshan._ 6b9fd1892SLinJiaweiimport utils._ 7cafb3558SLinJiaweiimport xiangshan.backend._ 8cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._ 9ccd5d342SGouLingruiimport xiangshan.backend.decode.isa._ 10cafb3558SLinJiawei 11cafb3558SLinJiaweiclass Jump extends FunctionUnit(jmpCfg){ 12cafb3558SLinJiawei val io = IO(new ExuIO) 13cafb3558SLinJiawei 14cafb3558SLinJiawei val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop) 15cafb3558SLinJiawei 16691af0f8SLinJiawei val redirectHit = uop.needFlush(io.redirect) 17cafb3558SLinJiawei val valid = iovalid && !redirectHit 18cafb3558SLinJiawei 19608ba82cSzhanglinjuan val isRVC = uop.cf.brUpdate.pd.isRVC 20cafb3558SLinJiawei val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U) 21cafb3558SLinJiawei val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 22cafb3558SLinJiawei 2312ff7156SLinJiawei io.out.bits.redirectValid := valid 24ccd5d342SGouLingrui io.out.bits.redirect.pc := uop.cf.pc 25cafb3558SLinJiawei io.out.bits.redirect.target := target 26cafb3558SLinJiawei io.out.bits.redirect.brTag := uop.brTag 27cafb3558SLinJiawei io.out.bits.redirect.isException := false.B 28*45a56a29SZhangZifei io.out.bits.redirect.isFlushPipe := false.B 29b2e6921eSLinJiawei io.out.bits.redirect.isMisPred := DontCare // check this in brq 30b2e6921eSLinJiawei io.out.bits.redirect.isReplay := false.B 3159d92720SLingrui98 io.out.bits.redirect.roqIdx := uop.roqIdx 32cafb3558SLinJiawei 33b2e6921eSLinJiawei io.out.bits.brUpdate := uop.cf.brUpdate 34608ba82cSzhanglinjuan io.out.bits.brUpdate.pc := uop.cf.pc 35608ba82cSzhanglinjuan io.out.bits.brUpdate.target := target 36b2e6921eSLinJiawei io.out.bits.brUpdate.brTarget := target // DontCare 37608ba82cSzhanglinjuan // io.out.bits.brUpdate.btbType := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable) 38b2e6921eSLinJiawei io.out.bits.brUpdate.taken := true.B 39608ba82cSzhanglinjuan // io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U //TODO: consider RVC 40b2e6921eSLinJiawei 41cafb3558SLinJiawei // Output 4212ff7156SLinJiawei val res = pcDelaySlot 43cafb3558SLinJiawei 44cafb3558SLinJiawei io.in.ready := io.out.ready 45cafb3558SLinJiawei io.out.valid := valid // TODO: CSR/MOU/FMV may need change it 46cafb3558SLinJiawei io.out.bits.uop <> io.in.bits.uop 47cafb3558SLinJiawei io.out.bits.data := res 48cafb3558SLinJiawei 4912ff7156SLinJiawei io.dmem <> DontCare 5012ff7156SLinJiawei io.out.bits.debug <> DontCare 5112ff7156SLinJiawei 52cafb3558SLinJiawei // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 53*45a56a29SZhangZifei XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d %d) brTag:%x\n", 5412ff7156SLinJiawei io.in.valid, 5512ff7156SLinJiawei io.in.ready, 5612ff7156SLinJiawei io.out.valid, 5712ff7156SLinJiawei io.out.ready, 5812ff7156SLinJiawei io.redirect.valid, 5912ff7156SLinJiawei io.redirect.bits.isException, 60*45a56a29SZhangZifei io.redirect.bits.isFlushPipe, 6112ff7156SLinJiawei redirectHit, 6212ff7156SLinJiawei io.redirect.bits.brTag.value 6312ff7156SLinJiawei ) 6412ff7156SLinJiawei XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 65cafb3558SLinJiawei} 66