xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala (revision 43ad9482848af9b861e38d775ef2a08c5b624dde)
1cafb3558SLinJiaweipackage xiangshan.backend.fu
2cafb3558SLinJiawei
3cafb3558SLinJiaweiimport chisel3._
4cafb3558SLinJiaweiimport chisel3.util._
5cafb3558SLinJiaweiimport xiangshan._
6b9fd1892SLinJiaweiimport utils._
7cafb3558SLinJiaweiimport xiangshan.backend._
8cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._
9ccd5d342SGouLingruiimport xiangshan.backend.decode.isa._
10cafb3558SLinJiawei
11e18c367fSLinJiaweitrait HasRedirectOut { this: RawModule =>
12e18c367fSLinJiawei  val redirectOutValid = IO(Output(Bool()))
13e18c367fSLinJiawei  val redirectOut = IO(Output(new Redirect))
14*43ad9482SLingrui98  val brUpdate = IO(Output(new CfiUpdateInfo))
15b2e234ebSLinJiawei}
16cafb3558SLinJiawei
1752c3f215SLinJiaweiclass Jump extends FunctionUnit with HasRedirectOut {
18cafb3558SLinJiawei
19e18c367fSLinJiawei  val (src1, offset, func, pc, uop) = (
20b2e234ebSLinJiawei    io.in.bits.src(0),
21b2e234ebSLinJiawei    io.in.bits.uop.ctrl.imm,
22b2e234ebSLinJiawei    io.in.bits.uop.ctrl.fuOpType,
23b2e234ebSLinJiawei    SignExt(io.in.bits.uop.cf.pc, AddrBits),
24b2e234ebSLinJiawei    io.in.bits.uop
25b2e234ebSLinJiawei  )
26b2e234ebSLinJiawei
273136ee6aSLinJiawei  val redirectHit = uop.roqIdx.needFlush(io.redirectIn)
28e18c367fSLinJiawei  val valid = io.in.valid && !redirectHit
29cafb3558SLinJiawei
30608ba82cSzhanglinjuan  val isRVC = uop.cf.brUpdate.pd.isRVC
31e18c367fSLinJiawei  val snpc = Mux(isRVC, pc + 2.U, pc + 4.U)
32cafb3558SLinJiawei  val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
33cafb3558SLinJiawei
34e18c367fSLinJiawei  redirectOutValid := valid
35b2e234ebSLinJiawei  redirectOut.pc := uop.cf.pc
36b2e234ebSLinJiawei  redirectOut.target := target
37b2e234ebSLinJiawei  redirectOut.brTag := uop.brTag
38b2e234ebSLinJiawei  redirectOut.isException := false.B
39b2e234ebSLinJiawei  redirectOut.isFlushPipe := false.B
40b2e234ebSLinJiawei  redirectOut.isMisPred := DontCare // check this in brq
41b2e234ebSLinJiawei  redirectOut.isReplay := false.B
42b2e234ebSLinJiawei  redirectOut.roqIdx := uop.roqIdx
43b2e234ebSLinJiawei
44b2e234ebSLinJiawei  brUpdate := uop.cf.brUpdate
45b2e234ebSLinJiawei  brUpdate.pc := uop.cf.pc
46b2e234ebSLinJiawei  brUpdate.target := target
47ae97381fSYinan Xu  brUpdate.brTarget := target
48b2e234ebSLinJiawei  brUpdate.taken := true.B
49b2e6921eSLinJiawei
50cafb3558SLinJiawei  // Output
51e18c367fSLinJiawei  val res = snpc
52cafb3558SLinJiawei
53cafb3558SLinJiawei  io.in.ready := io.out.ready
54e18c367fSLinJiawei  io.out.valid := valid
55cafb3558SLinJiawei  io.out.bits.uop <> io.in.bits.uop
56cafb3558SLinJiawei  io.out.bits.data := res
57cafb3558SLinJiawei
58cafb3558SLinJiawei  // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
5945a56a29SZhangZifei  XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d %d) brTag:%x\n",
6012ff7156SLinJiawei    io.in.valid,
6112ff7156SLinJiawei    io.in.ready,
6212ff7156SLinJiawei    io.out.valid,
6312ff7156SLinJiawei    io.out.ready,
64b2e234ebSLinJiawei    io.redirectIn.valid,
65b2e234ebSLinJiawei    io.redirectIn.bits.isException,
66b2e234ebSLinJiawei    io.redirectIn.bits.isFlushPipe,
6712ff7156SLinJiawei    redirectHit,
68b2e234ebSLinJiawei    io.redirectIn.bits.brTag.value
6912ff7156SLinJiawei  )
7012ff7156SLinJiawei  XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res)
71cafb3558SLinJiawei}
72