1cafb3558SLinJiaweipackage xiangshan.backend.fu 2cafb3558SLinJiawei 3cafb3558SLinJiaweiimport chisel3._ 4cafb3558SLinJiaweiimport chisel3.util._ 5cafb3558SLinJiaweiimport xiangshan._ 6cafb3558SLinJiaweiimport xiangshan.utils._ 7cafb3558SLinJiaweiimport xiangshan.backend._ 8cafb3558SLinJiaweiimport xiangshan.backend.fu.FunctionUnit._ 9cafb3558SLinJiawei 10cafb3558SLinJiaweiclass Jump extends FunctionUnit(jmpCfg){ 11cafb3558SLinJiawei val io = IO(new ExuIO) 12cafb3558SLinJiawei 13cafb3558SLinJiawei val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop) 14cafb3558SLinJiawei 15cafb3558SLinJiawei val redirectHit = uop.brTag.needFlush(io.redirect) 16cafb3558SLinJiawei val valid = iovalid && !redirectHit 17cafb3558SLinJiawei 18cafb3558SLinJiawei val isRVC = uop.cf.isRVC 19cafb3558SLinJiawei val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U) 20cafb3558SLinJiawei val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset) 21cafb3558SLinJiawei 22*12ff7156SLinJiawei io.out.bits.redirectValid := valid 23cafb3558SLinJiawei io.out.bits.redirect.target := target 24cafb3558SLinJiawei io.out.bits.redirect.brTag := uop.brTag 25cafb3558SLinJiawei io.out.bits.redirect.isException := false.B 26cafb3558SLinJiawei io.out.bits.redirect.roqIdx := uop.roqIdx 27cafb3558SLinJiawei io.out.bits.redirect.freelistAllocPtr := uop.freelistAllocPtr 28cafb3558SLinJiawei 29cafb3558SLinJiawei // Output 30*12ff7156SLinJiawei val res = pcDelaySlot 31cafb3558SLinJiawei 32cafb3558SLinJiawei io.in.ready := io.out.ready 33cafb3558SLinJiawei io.out.valid := valid // TODO: CSR/MOU/FMV may need change it 34cafb3558SLinJiawei io.out.bits.uop <> io.in.bits.uop 35cafb3558SLinJiawei io.out.bits.data := res 36cafb3558SLinJiawei 37*12ff7156SLinJiawei io.dmem <> DontCare 38*12ff7156SLinJiawei io.out.bits.debug <> DontCare 39*12ff7156SLinJiawei 40cafb3558SLinJiawei // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it 41cafb3558SLinJiawei XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x\n", 42*12ff7156SLinJiawei io.in.valid, 43*12ff7156SLinJiawei io.in.ready, 44*12ff7156SLinJiawei io.out.valid, 45*12ff7156SLinJiawei io.out.ready, 46*12ff7156SLinJiawei io.redirect.valid, 47*12ff7156SLinJiawei io.redirect.bits.isException, 48*12ff7156SLinJiawei redirectHit, 49*12ff7156SLinJiawei io.redirect.bits.brTag.value 50*12ff7156SLinJiawei ) 51*12ff7156SLinJiawei XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res) 52cafb3558SLinJiawei} 53