1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.WbArbiterParams 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.RdConfig._ 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.{FuConfig, FuType} 29import xiangshan.backend.issue._ 30import xiangshan.backend.regfile._ 31 32case class BackendParams( 33 schdParams : Map[SchedulerType, SchdBlockParams], 34 pregParams : Seq[PregParams], 35) { 36 37 configChecks 38 39 def intSchdParams = schdParams.get(IntScheduler()) 40 def vfSchdParams = schdParams.get(VfScheduler()) 41 def memSchdParams = schdParams.get(MemScheduler()) 42 def allSchdParams: Seq[SchdBlockParams] = 43 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 44 .filter(_.nonEmpty) 45 .map(_.get) 46 def allIssueParams: Seq[IssueBlockParams] = 47 allSchdParams.map(_.issueBlockParams).flatten 48 def allExuParams: Seq[ExeUnitParams] = 49 allIssueParams.map(_.exuBlockParams).flatten 50 51 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 52 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 53 54 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 55 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 56 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 57 58 59 def AluCnt = allSchdParams.map(_.AluCnt).sum 60 def StaCnt = allSchdParams.map(_.StaCnt).sum 61 def StdCnt = allSchdParams.map(_.StdCnt).sum 62 def LduCnt = allSchdParams.map(_.LduCnt).sum 63 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 64 def LsExuCnt = StaCnt + LduCnt 65 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 66 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 67 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 68 69 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 70 71 def numIntWb = intPregParams.numWrite 72 def numVfWb = vfPregParams.numWrite 73 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 74 def numExu = allSchdParams.map(_.numExu).sum 75 def numRfRead = 14 76 def numRfWrite = 8 77 def vconfigPort = 0 // Todo: remove it 78 79 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 80 81 def numRedirect = allSchdParams.map(_.numRedirect).sum 82 83 def genIntWriteBackBundle(implicit p: Parameters) = { 84 // Todo: limit write port 85 Seq.tabulate(numIntWb)(x => new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 86 } 87 88 def genVfWriteBackBundle(implicit p: Parameters) = { 89 // Todo: limit write port 90 Seq.tabulate(numVfWb)(x => new RfWritePortWithConfig(VecData(), intPregParams.addrWidth)) 91 } 92 93 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 94 genIntWriteBackBundle ++ genVfWriteBackBundle 95 } 96 97 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 98 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).reduce(_ ++ _)) 99 } 100 101 def getIntWbArbiterParams: WbArbiterParams = { 102 val intWbCfgs: Seq[WbConfig] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)) 103 datapath.WbArbiterParams(intWbCfgs, intPregParams) 104 } 105 106 def getVfWbArbiterParams: WbArbiterParams = { 107 val vfWbCfgs = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)) 108 datapath.WbArbiterParams(vfWbCfgs, vfPregParams) 109 } 110 111 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 112 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 113 114 def configChecks = { 115 // check 0 116 val maxPortSource = 2 117 118 allExuParams.map { 119 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 120 }.filter(_.isDefined).groupBy(_.get.port).foreach { 121 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 122 } 123 allExuParams.map { 124 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 125 }.filter(_.isDefined).groupBy(_.get.port).foreach { 126 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 127 } 128 129 // check 1 130 val wbTypes = Seq(IntWB(), VfWB()) 131 val rdTypes = Seq(IntRD(), VfRD()) 132 for(wbType <- wbTypes){ 133 for(rdType <- rdTypes){ 134 allExuParams.map { 135 case exuParam => 136 val wbPortConfigs = exuParam.wbPortConfigs 137 val wbConfigs = wbType match{ 138 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 139 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 140 case _ => None 141 } 142 val rfReadPortConfigs = exuParam.rfrPortConfigs 143 val rdConfigs = rdType match{ 144 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 145 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 146 case _ => Seq() 147 } 148 (wbConfigs, rdConfigs) 149 }.filter(_._1.isDefined) 150 .sortBy(_._1.get.priority) 151 .groupBy(_._1.get.port).map { 152 case (_, intWbRdPairs) => 153 intWbRdPairs.map(_._2).flatten 154 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 155 case (_, rdCfgs) => 156 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 157 }) 158 } 159 } 160 } 161} 162 163 164 165 166