1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30 31import scala.reflect.{ClassTag, classTag} 32 33case class BackendParams( 34 schdParams : Map[SchedulerType, SchdBlockParams], 35 pregParams : Seq[PregParams], 36 iqWakeUpParams : Seq[WakeUpConfig], 37) { 38 39 configChecks 40 41 def intSchdParams = schdParams.get(IntScheduler()) 42 def vfSchdParams = schdParams.get(VfScheduler()) 43 def memSchdParams = schdParams.get(MemScheduler()) 44 def allSchdParams: Seq[SchdBlockParams] = 45 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 46 .filter(_.nonEmpty) 47 .map(_.get) 48 def allIssueParams: Seq[IssueBlockParams] = 49 allSchdParams.map(_.issueBlockParams).flatten 50 def allExuParams: Seq[ExeUnitParams] = 51 allIssueParams.map(_.exuBlockParams).flatten 52 53 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 54 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 55 def getPregParams: Map[DataConfig, PregParams] = { 56 pregParams.map(x => (x.dataCfg, x)).toMap 57 } 58 59 def pregIdxWidth = pregParams.map(_.addrWidth).max 60 61 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 62 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 63 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 64 65 66 def AluCnt = allSchdParams.map(_.AluCnt).sum 67 def StaCnt = allSchdParams.map(_.StaCnt).sum 68 def StdCnt = allSchdParams.map(_.StdCnt).sum 69 def LduCnt = allSchdParams.map(_.LduCnt).sum 70 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 71 def LsExuCnt = StaCnt + LduCnt 72 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 73 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 74 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 75 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 76 77 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 78 def numTargetReadPort = allExuParams.count(x => x.needTarget) 79 80 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 81 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 82 83 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 84 def numExu = allSchdParams.map(_.numExu).sum 85 def vconfigPort = 0 // Todo: remove it 86 87 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 88 89 def numRedirect = allSchdParams.map(_.numRedirect).sum 90 91 def genIntWriteBackBundle(implicit p: Parameters) = { 92 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 93 } 94 95 def genVfWriteBackBundle(implicit p: Parameters) = { 96 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 97 } 98 99 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 100 genIntWriteBackBundle ++ genVfWriteBackBundle 101 } 102 103 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 104 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 105 } 106 107 def getIntWbArbiterParams: WbArbiterParams = { 108 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 109 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 110 } 111 112 def getVfWbArbiterParams: WbArbiterParams = { 113 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 114 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 115 } 116 117 /** 118 * Get regfile read port params 119 * 120 * @param dataCfg [[IntData]] or [[VecData]] 121 * @return Seq[port->Seq[(exuIdx, priority)] 122 */ 123 def getRdPortParams(dataCfg: DataConfig) = { 124 // port -> Seq[exuIdx, priority] 125 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 126 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 127 .filter { x => x._1.getDataConfig == dataCfg } 128 .map(x => (x._1.port, (x._2, x._1.priority))) 129 .groupBy(_._1) 130 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 131 .toSeq 132 .sortBy(_._1) 133 cfgs 134 } 135 136 /** 137 * Get regfile write back port params 138 * 139 * @param dataCfg [[IntData]] or [[VecData]] 140 * @return Seq[port->Seq[(exuIdx, priority)] 141 */ 142 def getWbPortParams(dataCfg: DataConfig) = { 143 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 144 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 145 .filter { x => x._1.dataCfg == dataCfg } 146 .map(x => (x._1.port, (x._2, x._1.priority))) 147 .groupBy(_._1) 148 .map(x => (x._1, x._2.map(_._2))) 149 .toSeq 150 .sortBy(_._1) 151 cfgs 152 } 153 154 def getRdPortIndices(dataCfg: DataConfig) = { 155 this.getRdPortParams(dataCfg).map(_._1) 156 } 157 158 def getWbPortIndices(dataCfg: DataConfig) = { 159 this.getWbPortParams(dataCfg).map(_._1) 160 } 161 162 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 163 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 164 _.exuBlockParams.map( 165 _.rfrPortConfigs.map( 166 _.collectFirst{ case x: T => x } 167 .getOrElse(NoRD()) 168 ) 169 ) 170 ) 171 rdCfgs 172 } 173 174 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 175 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 176 } 177 178 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 179 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 180 wbCfgs 181 } 182 183 /** 184 * Get size of read ports of int regfile 185 * 186 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 187 */ 188 def getIntRfReadSize = { 189 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 190 } 191 192 /** 193 * Get size of write ports of vf regfile 194 * 195 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 196 */ 197 def getIntRfWriteSize = { 198 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 199 } 200 201 /** 202 * Get size of read ports of int regfile 203 * 204 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 205 */ 206 def getVfRfReadSize = { 207 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 208 } 209 210 /** 211 * Get size of write ports of vf regfile 212 * 213 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 214 */ 215 def getVfRfWriteSize = { 216 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 217 } 218 219 def getRfReadSize(dataCfg: DataConfig) = { 220 this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 221 } 222 223 def getRfWriteSize(dataCfg: DataConfig) = { 224 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 225 } 226 227 def getExuIdx(name: String): Int = { 228 val exuParams = allExuParams 229 if (name != "WB") { 230 val foundExu = exuParams.find(_.name == name) 231 require(foundExu.nonEmpty, s"exu $name not find") 232 foundExu.get.exuIdx 233 } else 234 -1 235 } 236 237 def getExuName(idx: Int): String = { 238 val exuParams = allExuParams 239 exuParams(idx).name 240 } 241 242 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 243 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 244 245 private def isContinuous(portIndices: Seq[Int]): Boolean = { 246 val portIndicesSet = portIndices.toSet 247 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 248 } 249 250 def configChecks = { 251 checkReadPortContinuous 252 checkWritePortContinuous 253 configCheck 254 } 255 256 def checkReadPortContinuous = { 257 pregParams.foreach { x => 258 if (x.numRead.isEmpty) { 259 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 260 require(isContinuous(portIndices), 261 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 262 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 263 } 264 } 265 } 266 267 def checkWritePortContinuous = { 268 pregParams.foreach { x => 269 if (x.numWrite.isEmpty) { 270 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 271 require( 272 isContinuous(portIndices), 273 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 274 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 275 ) 276 } 277 } 278 } 279 280 def configCheck = { 281 // check 0 282 val maxPortSource = 4 283 284 allExuParams.map { 285 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 286 }.filter(_.isDefined).groupBy(_.get.port).foreach { 287 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 288 } 289 allExuParams.map { 290 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 291 }.filter(_.isDefined).groupBy(_.get.port).foreach { 292 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 293 } 294 295 // check 1 296 val wbTypes = Seq(IntWB(), VfWB()) 297 val rdTypes = Seq(IntRD(), VfRD()) 298 for(wbType <- wbTypes){ 299 for(rdType <- rdTypes){ 300 allExuParams.map { 301 case exuParam => 302 val wbPortConfigs = exuParam.wbPortConfigs 303 val wbConfigs = wbType match{ 304 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 305 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 306 case _ => None 307 } 308 val rfReadPortConfigs = exuParam.rfrPortConfigs 309 val rdConfigs = rdType match{ 310 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 311 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 312 case _ => Seq() 313 } 314 (wbConfigs, rdConfigs) 315 }.filter(_._1.isDefined) 316 .sortBy(_._1.get.priority) 317 .groupBy(_._1.get.port).map { 318 case (_, intWbRdPairs) => 319 intWbRdPairs.map(_._2).flatten 320 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 321 case (_, rdCfgs) => 322 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 323 }) 324 } 325 } 326 } 327} 328 329 330 331 332