1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.{DebugOptionsKey, XSCoreParamsKey} 31 32import scala.collection.mutable 33import scala.reflect.{ClassTag, classTag} 34 35case class BackendParams( 36 schdParams : Map[SchedulerType, SchdBlockParams], 37 pregParams : Seq[PregParams], 38 iqWakeUpParams : Seq[WakeUpConfig], 39) { 40 41 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 42 43 val copyPdestInfo = mutable.HashMap[Int, (Int, Int)]() 44 45 def updateCopyPdestInfo: Unit = allExuParams.filter(_.copyWakeupOut).map(x => getExuIdx(x.name) -> (x.copyDistance, -1)).foreach { x => 46 copyPdestInfo.addOne(x) 47 } 48 def isCopyPdest(exuIdx: Int): Boolean = { 49 copyPdestInfo.contains(exuIdx) 50 } 51 def connectWakeup(exuIdx: Int): Unit = { 52 println(s"[Backend] copyPdestInfo ${copyPdestInfo}") 53 if (copyPdestInfo.contains(exuIdx)) { 54 println(s"[Backend] exuIdx ${exuIdx} be connected, old info ${copyPdestInfo(exuIdx)}") 55 val newInfo = exuIdx -> (copyPdestInfo(exuIdx)._1, copyPdestInfo(exuIdx)._2 + 1) 56 copyPdestInfo.remove(exuIdx) 57 copyPdestInfo += newInfo 58 println(s"[Backend] exuIdx ${exuIdx} be connected, new info ${copyPdestInfo(exuIdx)}") 59 } 60 } 61 def getCopyPdestIndex(exuIdx: Int): Int = { 62 copyPdestInfo(exuIdx)._2 / copyPdestInfo(exuIdx)._1 63 } 64 def intSchdParams = schdParams.get(IntScheduler()) 65 def fpSchdParams = schdParams.get(FpScheduler()) 66 def vfSchdParams = schdParams.get(VfScheduler()) 67 def memSchdParams = schdParams.get(MemScheduler()) 68 def allSchdParams: Seq[SchdBlockParams] = 69 (Seq(intSchdParams) :+ fpSchdParams :+ vfSchdParams :+ memSchdParams) 70 .filter(_.nonEmpty) 71 .map(_.get) 72 def allIssueParams: Seq[IssueBlockParams] = 73 allSchdParams.map(_.issueBlockParams).flatten 74 def allExuParams: Seq[ExeUnitParams] = 75 allIssueParams.map(_.exuBlockParams).flatten 76 77 // filter not fake exu unit 78 def allRealExuParams = 79 allExuParams.filterNot(_.fakeUnit) 80 81 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 82 def fpPregParams: FpPregParams = pregParams.collectFirst { case x: FpPregParams => x }.get 83 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 84 def getPregParams: Map[DataConfig, PregParams] = { 85 pregParams.map(x => (x.dataCfg, x)).toMap 86 } 87 88 def pregIdxWidth = pregParams.map(_.addrWidth).max 89 90 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 91 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 92 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 93 94 95 def AluCnt = allSchdParams.map(_.AluCnt).sum 96 def StaCnt = allSchdParams.map(_.StaCnt).sum 97 def StdCnt = allSchdParams.map(_.StdCnt).sum 98 def LduCnt = allSchdParams.map(_.LduCnt).sum 99 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 100 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 101 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 102 def LsExuCnt = StaCnt + LduCnt + HyuCnt 103 val LdExuCnt = LduCnt + HyuCnt 104 val StaExuCnt = StaCnt + HyuCnt 105 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 106 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 107 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 108 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 109 110 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 111 def numPcMemReadPort = allExuParams.filter(_.needPc).size 112 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 113 114 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 115 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 116 117 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 118 def numExu = allSchdParams.map(_.numExu).sum 119 120 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 121 122 def numRedirect = allSchdParams.map(_.numRedirect).sum 123 124 def numLoadDp = memSchdParams.get.issueBlockParams.filter(x => x.isLdAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 125 126 def numStoreDp = memSchdParams.get.issueBlockParams.filter(x => x.isStAddrIQ || x.isHyAddrIQ).map(_.numEnq).sum 127 128 def genIQValidNumBundle(implicit p: Parameters) = { 129 this.intSchdParams.get.issueBlockParams.map(x => Vec(x.numDeq, UInt((x.numEntries).U.getWidth.W))) 130 } 131 132 def genIntWriteBackBundle(implicit p: Parameters) = { 133 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 134 } 135 136 def genFpWriteBackBundle(implicit p: Parameters) = { 137 Seq.fill(this.getFpRfWriteSize)(new RfWritePortWithConfig(FpData(), fpPregParams.addrWidth)) 138 } 139 140 def genVfWriteBackBundle(implicit p: Parameters) = { 141 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 142 } 143 144 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 145 genIntWriteBackBundle ++ genVfWriteBackBundle 146 } 147 148 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 149 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 150 } 151 152 def getIntWbArbiterParams: WbArbiterParams = { 153 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 154 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 155 } 156 157 def getVfWbArbiterParams: WbArbiterParams = { 158 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec)).map(_.asInstanceOf[VfWB]) 159 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 160 } 161 162 def getFpWbArbiterParams: WbArbiterParams = { 163 val fpWbCfgs: Seq[FpWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeFp)).map(_.asInstanceOf[FpWB]) 164 datapath.WbArbiterParams(fpWbCfgs, vfPregParams, this) 165 } 166 167 /** 168 * Get regfile read port params 169 * 170 * @param dataCfg [[IntData]] or [[VecData]] 171 * @return Seq[port->Seq[(exuIdx, priority)] 172 */ 173 def getRdPortParams(dataCfg: DataConfig) = { 174 // port -> Seq[exuIdx, priority] 175 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 176 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 177 .filter { x => x._1.getDataConfig == dataCfg } 178 .map(x => (x._1.port, (x._2, x._1.priority))) 179 .groupBy(_._1) 180 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 181 .toSeq 182 .sortBy(_._1) 183 cfgs 184 } 185 186 /** 187 * Get regfile write back port params 188 * 189 * @param dataCfg [[IntData]] or [[VecData]] 190 * @return Seq[port->Seq[(exuIdx, priority)] 191 */ 192 def getWbPortParams(dataCfg: DataConfig) = { 193 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 194 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 195 .filter { x => x._1.dataCfg == dataCfg } 196 .map(x => (x._1.port, (x._2, x._1.priority))) 197 .groupBy(_._1) 198 .map(x => (x._1, x._2.map(_._2))) 199 .toSeq 200 .sortBy(_._1) 201 cfgs 202 } 203 204 def getRdPortIndices(dataCfg: DataConfig) = { 205 this.getRdPortParams(dataCfg).map(_._1) 206 } 207 208 def getWbPortIndices(dataCfg: DataConfig) = { 209 this.getWbPortParams(dataCfg).map(_._1) 210 } 211 212 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 213 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 214 _.exuBlockParams.map( 215 _.rfrPortConfigs.map( 216 _.collectFirst{ case x: T => x } 217 .getOrElse(NoRD()) 218 ) 219 ) 220 ) 221 rdCfgs 222 } 223 224 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 225 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 226 } 227 228 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 229 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 230 wbCfgs 231 } 232 233 /** 234 * Get size of read ports of int regfile 235 * 236 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 237 */ 238 def getIntRfReadSize = { 239 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 240 } 241 242 /** 243 * Get size of write ports of vf regfile 244 * 245 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 246 */ 247 def getIntRfWriteSize = { 248 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 249 } 250 251 /** 252 * Get size of write ports of fp regfile 253 * 254 * @return if [[FpPregParams.numWrite]] is [[None]], get size of ports in [[FpWB]] 255 */ 256 def getFpRfWriteSize = { 257 this.fpPregParams.numWrite.getOrElse(this.getWbPortIndices(FpData()).size) 258 } 259 260 /** 261 * Get size of read ports of int regfile 262 * 263 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 264 */ 265 def getVfRfReadSize = { 266 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 267 } 268 269 /** 270 * Get size of write ports of vf regfile 271 * 272 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 273 */ 274 def getVfRfWriteSize = { 275 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 276 } 277 278 def getRfReadSize(dataCfg: DataConfig) = { 279 dataCfg match{ 280 case IntData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 281 case FpData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 282 case VecData() => this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 283 } 284 } 285 286 def getRfWriteSize(dataCfg: DataConfig) = { 287 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 288 } 289 290 def getExuIdx(name: String): Int = { 291 val exuParams = allRealExuParams 292 if (name != "WB") { 293 val foundExu = exuParams.find(_.name == name) 294 require(foundExu.nonEmpty, s"exu $name not find") 295 foundExu.get.exuIdx 296 } else 297 -1 298 } 299 300 def getExuName(idx: Int): String = { 301 val exuParams = allRealExuParams 302 exuParams(idx).name 303 } 304 305 def getExuParamByName(name: String): ExeUnitParams = { 306 val exuParams = allExuParams 307 exuParams.find(_.name == name).get 308 } 309 310 def getLdExuIdx(exu: ExeUnitParams): Int = { 311 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 312 ldExuParams.indexOf(exu) 313 } 314 315 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 316 def getFpWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getFpWBPort.getOrElse(FpWB(port = -1)).port).filter(_._1 != -1) 317 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 318 319 private def isContinuous(portIndices: Seq[Int]): Boolean = { 320 val portIndicesSet = portIndices.toSet 321 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 322 } 323 324 def configChecks = { 325 checkReadPortContinuous 326 checkWritePortContinuous 327 configCheck 328 } 329 330 def checkReadPortContinuous = { 331 pregParams.filterNot(_.isFake).foreach { x => 332 if (x.numRead.isEmpty) { 333 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 334 require(isContinuous(portIndices), 335 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 336 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 337 } 338 } 339 } 340 341 def checkWritePortContinuous = { 342 pregParams.filterNot(_.isFake).foreach { x => 343 if (x.numWrite.isEmpty) { 344 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 345 require( 346 isContinuous(portIndices), 347 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 348 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 349 ) 350 } 351 } 352 } 353 354 def configCheck = { 355 // check 0 356 val maxPortSource = 4 357 358 allRealExuParams.map { 359 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 360 }.filter(_.isDefined).groupBy(_.get.port).foreach { 361 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 362 } 363 allRealExuParams.map { 364 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 365 }.filter(_.isDefined).groupBy(_.get.port).foreach { 366 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 367 } 368 369 // check 1 370 // if some exus share the same wb port and rd ports, 371 // the exu with high priority at wb must also have high priority at rd. 372 val wbTypes = Seq(IntWB(), FpWB(), VfWB()) 373 val rdTypes = Seq(IntRD(), FpRD(), VfRD()) 374 for(wbType <- wbTypes){ 375 for(rdType <- rdTypes){ 376 println(s"[BackendParams] wbType: ${wbType}, rdType: ${rdType}") 377 allRealExuParams.map { 378 case exuParam => 379 val wbPortConfigs = exuParam.wbPortConfigs 380 val wbConfigs = wbType match{ 381 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 382 case _: FpWB => wbPortConfigs.collectFirst { case x: FpWB => x } 383 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 384 case _ => None 385 } 386 val rfReadPortConfigs = exuParam.rfrPortConfigs 387 val rdConfigs = rdType match{ 388 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 389 case _: FpRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[FpRD]) 390 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 391 case _ => Seq() 392 } 393 (wbConfigs, rdConfigs) 394 }.filter(_._1.isDefined) 395 .sortBy(_._1.get.priority) 396 .groupBy(_._1.get.port).map { case (wbPort, intWbRdPairs) => 397 val rdCfgs = intWbRdPairs.map(_._2).flatten 398 println(s"[BackendParams] wb port ${wbPort} rdcfgs: ${rdCfgs}") 399 rdCfgs.groupBy(_.port).foreach { case (p, rdCfg) => 400 //println(s"[BackendParams] rdport: ${p}, cfgs: ${rdCfg}") 401 rdCfg.zip(rdCfg.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority, s"an exu has high priority at ${wbType} wb port ${wbPort}, but has low priority at ${rdType} rd port ${p}") } 402 } 403 } 404 } 405 } 406 } 407} 408