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Searched +full:jh7110 +full:- +full:crg (Results 1 – 14 of 14) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dstarfive,jh7110-voutcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10 - Xingyu Wu <[email protected]>
14 const: starfive,jh7110-voutcrg
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
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Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <[email protected]>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
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Dstarfive,jh7110-stgcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
10 - Xingyu Wu <[email protected]>
14 const: starfive,jh7110-stgcrg
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
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Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <[email protected]>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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Dstarfive,jh7110-syscrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System Clock and Reset Generator
10 - Emil Renner Berthing <[email protected]>
14 const: starfive,jh7110-syscrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
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Dstarfive,jh7110-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
13 SYS-SYSCON node.
18 - Xingyu Wu <[email protected]>
22 const: starfive,jh7110-pll
28 '#clock-cells':
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/linux-6.14.4/drivers/reset/starfive/
Dreset-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7110 SoC
10 #include <soc/starfive/reset-starfive-jh71x0.h>
12 #include "reset-starfive-jh71x0.h"
14 #include <dt-bindings/reset/starfive,jh7110-crg.h>
55 struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data); in jh7110_reset_probe()
57 void __iomem *base = rdev->base; in jh7110_reset_probe()
60 return -ENODEV; in jh7110_reset_probe()
62 return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node, in jh7110_reset_probe()
63 base + info->assert_offset, in jh7110_reset_probe()
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/linux-6.14.4/drivers/clk/starfive/
Dclk-starfive-jh7110-aon.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 Always-On Clock Driver
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/starfive,jh7110-crg.h>
15 #include "clk-starfive-jh7110.h"
63 priv = devm_kzalloc(&pdev->dev, in jh7110_aoncrg_probe()
67 return -ENOMEM; in jh7110_aoncrg_probe()
69 spin_lock_init(&priv->rmw_lock); in jh7110_aoncrg_probe()
70 priv->num_reg = JH7110_AONCLK_END; in jh7110_aoncrg_probe()
71 priv->dev = &pdev->dev; in jh7110_aoncrg_probe()
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Dclk-starfive-jh7110-stg.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 System-Top-Group Clock Driver
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/starfive,jh7110-crg.h>
15 #include "clk-starfive-jh7110.h"
40 /* pci-e */
84 priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END), in jh7110_stgcrg_probe()
87 return -ENOMEM; in jh7110_stgcrg_probe()
89 spin_lock_init(&priv->rmw_lock); in jh7110_stgcrg_probe()
90 priv->num_reg = JH7110_STGCLK_END; in jh7110_stgcrg_probe()
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Dclk-starfive-jh7110-isp.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 Image-Signal-Process Clock Driver
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/starfive,jh7110-crg.h>
17 #include "clk-starfive-jh7110.h"
70 top_rsts = devm_reset_control_array_get_shared(priv->dev); in jh7110_isp_top_rst_init()
72 return dev_err_probe(priv->dev, PTR_ERR(top_rsts), in jh7110_isp_top_rst_init()
83 clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); in jh7110_ispcrg_suspend()
92 return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); in jh7110_ispcrg_resume()
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Dclk-starfive-jh7110-vout.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 Video-Output Clock Driver
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/starfive,jh7110-crg.h>
17 #include "clk-starfive-jh7110.h"
76 top_rst = devm_reset_control_get_shared(priv->dev, NULL); in jh7110_vout_top_rst_init()
78 return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n"); in jh7110_vout_top_rst_init()
88 clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); in jh7110_voutcrg_suspend()
97 return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); in jh7110_voutcrg_resume()
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Dclk-starfive-jh7110-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
22 #include <linux/clk-provider.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
275 return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]); in jh7110_pll_priv_from()
284 regmap_read(regmap, info->offsets.pd, &val); in jh7110_pll_regvals_get()
285 ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; in jh7110_pll_regvals_get()
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Dclk-starfive-jh7110-sys.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 System Clock Driver
11 #include <linux/clk-provider.h>
17 #include <soc/starfive/reset-starfive-jh71x0.h>
19 #include <dt-bindings/clock/starfive,jh7110-crg.h>
21 #include "clk-starfive-jh7110.h"
352 return -ENOMEM; in jh7110_reset_controller_register()
354 rdev->base = priv->base; in jh7110_reset_controller_register()
356 adev = &rdev->adev; in jh7110_reset_controller_register()
357 adev->name = adev_name; in jh7110_reset_controller_register()
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/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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